Abstract: Provided are a flash memory device and a method of fabricating the same. The method includes forming a first dielectric layer on an active region of a semiconductor substrate. A first conductive layer is formed on the semiconductor substrate having the first dielectric layer. A mask pattern is formed on the first conductive layer. Using the mask pattern as an etch mask, the first conductive layer is etched to form a first conductive pattern narrowing from its upper surface toward its middle portion. A second dielectric layer is formed on the semiconductor substrate having the first conductive pattern. A second conductive pattern crossing the active region adjacent to the first conductive pattern and partially covering the first conductive pattern is formed on the semiconductor substrate having the second dielectric layer.

Abstract: A nonvolatile memory device includes first and second impurity diffusion regions formed in a semiconductor substrate, and a memory cell formed on a channel region of a semiconductor substrate between the first and second impurity diffusion regions. The memory cell includes a stacked gate structure formed on the channel region, and first and second select gates formed on the channel regions and opposite sidewalls of the stacked gate structure. Since the first and second select gates are spacer-shaped to be self-aligned on opposite sidewalls of the stacked gate structure, a size of a memory cell is reduced to enhance an integration density of a semiconductor device.

Abstract: In a split gate type nonvolatile memory device, a supplementary layer pattern is disposed on a source region of a semiconductor substrate. Since the source region is vertically extended by virtue of the presence of the supplementary layer pattern, it is therefore possible to increase an area of a region where a floating gate overlaps the source region and the supplementary layer pattern. Accordingly, the capacitance of a capacitor formed between the source and the floating gate increases so that it is possible for the nonvolatile memory device to perform program/erase operations at a low voltage level.

Abstract: A nonvolatile semiconductor device and a method of fabricating the same are provided. The nonvolatile semiconductor device includes a semiconductor body formed on a substrate to be elongated in one direction and having a cross section perpendicular to a main surface of the substrate and elongated direction, the cross section having a predetermined curvature, a channel region partially formed along the circumference of the semiconductor body, a tunneling insulating layer disposed on the channel region, a floating gate disposed on the tunneling insulating layer and electrically insulated from the channel region, an intergate insulating layer disposed on the floating gate, a control gate disposed on the intergate insulating layer and electrically insulated from the floating gate, and source and drain regions which are aligned with both sides of the control gate and formed within the semiconductor body.

Abstract: Example embodiments relate to a non-volatile memory device and a method of forming the same. A non-volatile memory device according to example embodiments may include a conductive pattern provided on the semiconductor substrate. A tunnel insulator may be provided on the conductive pattern. A memory gate structure may be provided on the semiconductor substrate so as to cover a first end of the conductive pattern. The first end may include an upward tapering, first protrusion. A select gate structure may be provided on the semiconductor substrate so as to cover the second end of the conductive pattern. The second end may include an upward tapering, second protrusion. The coverage of the first protrusion by the memory gate structure may be greater than the coverage of the second protrusion by the select gate structure.

Abstract: A split-gate non-volatile memory device includes a raised oxide layer on a field oxide region between adjacent split-gate memory cells, the raised oxide layer extending onto first and second floating gates included in the adjacent split-gate memory cells covered by a wordline electrically coupled to respective control gates included in the adjacent split-gate memory cells.

Abstract: A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.

Abstract: A nonvolatile memory (NVM) device includes a floating gate on a semiconductor substrate and a gate insulating layer between the semiconductor substrate and the floating gate. A tunnel insulating layer is disposed between the semiconductor substrate and the floating gate. The tunnel insulating layer is thinner than the gate insulating layer. A first inter-gate insulating layer is disposed on the floating gate, and a sensing gate is disposed on the first inter-gate insulating layer. The sensing gate covers a first portion of the floating gate. A control gate is disposed to cover a top surface and a sidewall of a second portion of the floating gate. A second inter-gate insulating layer is disposed between the control gate and the sensing gate and between the control gate and the floating gate. Operation methods and fabrication methods of the NVM device are also provided.

Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Abstract: A non-volatile memory device comprises a semiconductor substrate having source/drain regions formed at both ends of a channel region, a gate structure forming an offset region by being separated a predetermined distance from the source region and comprising a charge accumulation region and a control gate sequentially deposited in the channel region to at least partially overlap the drain region, and a spacer arranged at each of both side walls of the gate structure. A threshold voltage value of the offset region changes depending on a dielectric constant of the spacer.

Abstract: A non-volatile memory device includes a first sensing line, a first word line, a depletion channel region, and impurity regions. The first sensing line and the first word line are formed adjacent to each other in parallel on a substrate. The first sensing line and the first word line have a tunnel oxide layer, a first conductive pattern, a dielectric layer pattern and a second conductive pattern sequentially stacked on the substrate. The depletion channel region is formed at an upper portion of the substrate under the first sensing line. The impurity regions are formed at upper portions of the substrate exposed by the first sensing line and the first word line.

Abstract: Example embodiments are directed to a mask ROM, a mask ROM embedded EEPROM and a method of fabricating the same. The mask ROM may include a select gate pattern and a memory gate pattern disposed between a source region and a drain region at each of the on-cell and the off-cell. The on-cell may include a cell diffusion region between the select gate pattern and the memory gate pattern.

Abstract: A non-volatile integrated circuit memory device may include a semiconductor substrate having first and second electrically isolated wells of a same conductivity type. A first plurality of non-volatile memory cell transistors may be provided on the first well, and a second plurality of non-volatile memory cell transistors may be provided on the second well. A local control gate line may be electrically coupled with the first and second pluralities of non-volatile memory cell transistors, and a group selection transistor may be electrically coupled between the local control gate line and a global control gate line. More particularly, the group selection transistor may be configured to electrically couple and decouple the local control gate line and the global control gate line responsive to a group selection gate signal applied to a gate of the group selection transistor. Related methods and systems are also discussed.

Abstract: A method of forming a split-gate non-volatile memory cell can include forming first and second adjacent floating gates self-aligned to a field oxide region therebetween. An oxide layer is formed covering the first and second adjacent floating gates and the field oxide region, the oxide layer electrically isolates the first and second adjacent floating gates from one another. A control gate is formed on the oxide layer on the first and second adjacent floating gates. Related devices are also disclosed.

Abstract: An electrically erasable and programmable read only memory (EEPROM) device and a method of manufacturing the EEPROM device are provided. First and second gate structures having the same structure are formed on a tunnel insulating layer formed on a substrate, such that the first and second gate structures are spaced apart from each other. A common source region is formed at a portion of the substrate located between the first and second gate structures. First and second drain regions are formed at first and second portions of the substrate adjacent to the first and second gate structures, respectively. Thus, the EEPROM device is manufactured including first and second transistors that have the same structure and may alternately serve as a memory transistor and a selection transistor according to an applied signal.

Abstract: In one embodiment, a semiconductor device includes a semiconductor substrate having a first junction region and a second junction region. An insulated floating gate is disposed on the substrate. The floating gate at least partially overlaps the first junction region. An insulated program gate is disposed on the floating gate. The program gate has a curved upper surface. The semiconductor device further includes an insulated erase gate disposed on the substrate and adjacent the floating gate. The erase gate partially overlaps the second junction region.

Abstract: A device is described comprising a substrate of a first conductivity type having a first dopant concentration, a first well formed in the substrate, a second well of the first conductivity type formed in the substrate and being deeper than the first well, the second well having a higher dopant concentration than the first dopant concentration, and a nonvolatile memory cell formed on the second well. A device is described comprising four wells of various conductivity types with a nonvolatile memory cell formed on the second well. A device is described comprising a plurality of wells for isolating transistors of a plurality of voltage ranges, wherein each one of the plurality of wells contains at least one transistor of a particular voltage range, and wherein transistors of only one of the plurality of voltage ranges are within each of the plurality of wells.

Abstract: Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

Abstract: A mask read-only memory (ROM) cell, a method for fabricating the mask ROM cell, a NOR-type mask ROM device, and a method for fabricating the NOR-type mask ROM device are disclosed. A mask ROM cell includes a substrate including an ON cell region and an OFF cell region, a first gate electrode disposed in the ON cell region, and a second gate electrode disposed in the OFF cell region. The mask ROM cell also includes a first impurity region disposed in the substrate proximate a sidewall of the first gate electrode, wherein a portion of the first impurity region is disposed under the first gate electrode; and a second impurity region disposed the substrate proximate a sidewall of the second gate electrode, wherein no portion of the second impurity region is disposed under the second gate electrode.

Abstract: An electrically erasable programmable read-only memory (EEPROM) device includes an EEPROM cell located on a semiconductor substrate, the EEPROM cell including a memory transistor and a selection transistor. A source region and a drain region are located on the semiconductor substrate adjacent to opposite sides of the EEPROM cell, respectively, and a floating region is positioned between the memory transistor and the selection transistor. The source region includes a first doped region, a second doped region and a third doped region, where the first doped region surrounds a bottom surface and sidewalls of the second doped region, and the second doped surrounds a bottom surface and sidewalls of the third doped region. Also, a second impurity concentration of the second doped region is higher than that of the first doped region and lower than that of the third doped region.