Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: An image sensor and a method for manufacturing the same are provided. In the method, a photoresist is formed on a substrate including a photodiode region and a gate electrode opposite to the photodiode region on the basis of the gate electrode. An oxide layer is formed to a specific thickness on both the photodiode region and a part of the gate electrode. The photoresist is removed from the substrate and cleaned. A first oxide film is formed on the substrate, the gate electrode, and the oxide layer remaining on the photodiode region. A nitride film is formed on the first oxide film. And a second oxide film is formed on the nitride film. Blank etching is performed on the first oxide film, the nitride film, and the second oxide film to form a spacer at the side of the gate electrode.

Abstract: A method for fabricating a semiconductor transistor which eliminates device defects generated during an etching process for forming gates. The method may include laminating an ONO layer on and/or over a semiconductor substrate, and then coating a polysilicon layer on and/or over the ONO layer, and then forming a photoresist pattern on and/or over the polysilicon layer, and then sequentially performing a first etching of the polysilicon layer using the photoresist pattern as an etching mask so as to maintain a predetermined thickness of the polysilicon layer and then a second etching to remove the polysilicon layer remaining from the first etching.

Abstract: A semiconductor device can include a first interlayer dielectric layer disposed on a substrate, and an air gap defined in a portion of the first interlayer dielectric layer. The air gap can be formed within trenches etched into the first interlayer dielectric layer. An etch stop layer is disposed on the first interlayer dielectric layer and the air gap, and includes a hole communicating with the air gap.

Abstract: A method for manufacturing a semiconductor device includes: forming a device isolation layer in a semiconductor substrate; forming a gate insulating layer and a gate electrode on the semiconductor substrate; depositing a triple layer over the resulting structure, the triple layer including a bottom oxide layer, a nitride oxide layer and a top oxide layer; and etching the triple layer to form spacers.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device that may improve a reliability of process by obtaining a Depth of Focus (DOF) in an exposure process. In embodiments, a method may include sequentially stacking an oxide film, a floating gate poly film, an ONO film, a control gate poly film, and a BARC (Bottom AntiReflect Coating) on a semiconductor substrate, forming a photoresist pattern for a stack gate on the BARC, and etching the BARC, the control gate poly film, the ONO film and the floating gate poly film at once by using the photoresist pattern until the oxide film is exposed.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a polysilicon layer on a semiconductor substrate, forming an anti-reflection coating on the polysilicon layer, forming a photoresist (PR) layer pattern on the anti-reflection coating, etching the anti-reflection coating using the PR layer pattern as a mask in capacitive coupled plasma (CCP) equipment using CF4, Ar, and O2, so as to cause a reaction by-product generated by etching the anti-reflect coating to be deposited on sidewalls of the PR layer pattern, thereby forming spacers, and etching the polysilicon layer using the PR layer pattern and the spacers as a mask.

Abstract: There is provided a method of forming a damascene pattern including a via and a trench in a damascene process of forming a copper metal interconnection. The method includes forming an interlayer dielectric layer on a substrate, forming a first photosensitive layer pattern including a first opening that exposes a region in which a via is to be formed on the interlayer dielectric layer, etching the interlayer dielectric layer to a first depth using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern and forming a second photosensitive layer pattern including a second opening that exposes a region in which a trench is to be formed on the interlayer dielectric layer, and etching the interlayer dielectric layer using the second photosensitive layer pattern as an etching mask to simultaneously form the via and the trench.

Abstract: An image sensor includes a readout circuitry, a first substrate, a first interlayer dielectric, a metal interconnection, a top metal, and an image sensing device. The readout circuitry is formed on and/or over the first substrate and the first interlayer dielectric is formed on and/or over the first substrate. The metal interconnection is formed in the interlayer dielectric and electrically connected to the readout circuitry. The top metal is formed on and/or over the metal interconnection and the image sensing device is formed on and/or over the top metal.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: Provided are a semiconductor device and a method of manufacturing the same. In the method, a metal interconnection can be formed on a substrate. A dielectric can be formed on the metal interconnection. A photoresist pattern can be formed on the dielectric. The dielectric can be etched using the photoresist pattern as an etch mask to form a dense region of contact holes exposing the metal interconnection and dummy patterns surrounding the region of contact holes. In the semiconductor device, the dummy patterns are disposed around the dense contact holes to minimize a difference between etching rates of the contact holes, thereby inhibiting an etching defect such as an under-etch or over-etch defect.

Abstract: A method for manufacturing a semiconductor device includes that can prevent formation of fences of reaction by-products around chain holes during a dual damascene process, so subsequent metal gap fill defects are prevented, making it possible to prevent device failure. The method may include forming a via hole in an interlayer insulating layer exposing a bottom anti-reflection coating, and then filling the via hole with a first material, and then removing a portion of the first material, and then forming an oxide film over the first material to refill the via hole, and then forming a trench by etching the interlayer insulating layer and the oxide film, and then opening the via hole by removing the first material in the via hole to the bottom anti-reflection coating, and then etching the bottom anti-reflection coating to expose the metal wire, and then filling the opened via hole and trench with metal.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: A method of fabricating a floating gate of a flash memory device is provided. The method includes: forming a tunneling oxide layer on a substrate; forming a conductive thin layer on the tunneling oxide layer; applying a photoresist on the conductive thin layer; defining a floating gate region by patterning the photoresist; forming polymer sidewalls on the sides of the patterned photoresist; and selectively removing the conductive thin layer using the photoresist and the polymer sidewalls as a mask to form a floating gate.

Abstract: A method for fabricating a semiconductor transistor which eliminates device defects generated during an etching process for forming gates. The method may include laminating an ONO layer on and/or over a semiconductor substrate, and then coating a polysilicon layer on and/or over the ONO layer, and then forming a photoresist pattern on and/or over the polysilicon layer, and then sequentially performing a first etching of the polysilicon layer using the photoresist pattern as an etching mask so as to maintain a predetermined thickness of the polysilicon layer and then a second etching to remove the polysilicon layer remaining from the first etching.

Abstract: Method for fabricating a semiconductor device in which a by-product of etching is deposited on a photoresist film for using as a mask. The method for fabricating a semiconductor device includes the steps of depositing a polysilicon, and a bottom anti-refection coating on an entire surface of a substrate in succession, forming a photoresist film pattern on a predetermined portion of the bottom anti-refection coating, etching the bottom anti-refection coating by using the photoresist film pattern to deposit by-product of the etching on sidewalls of the photoresist pattern to form spacers, and etching the polysilicon by using the photoresist film pattern and the spacers, to form a line.

Abstract: A flash memory device fabricating method can include forming a plurality of gate patterns over a semiconductor substrate, forming a first spacer over the semiconductor substrate and against sidewalls of each gate pattern and a second spacer over the first spacer, forming an impurity region in the semiconductor substrate and between respective gate patterns, removing the second spacer, and then forming a pre-metal dielectric film over the semiconductor substrate including the gate patterns and the first spacer. The second space can be removed in order to expand a space between the gate patterns to thereby prevent generation of voids between the gate patterns.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device, which may increase a coupling coefficient between a control gate and a floating gate by increasing a surface area of floating gate. In embodiments, a flash memory device may be formed by forming a photoresist pattern for forming a floating gate on a semiconductor substrate including an oxide film, a floating gate poly film, and a BARC (Bottom AntiReflect Coating), performing a first etching process using the photoresist pattern as a mask, to etch the floating gate poly film to a predetermined depth, depositing and forming a polymer to cover the photoresist pattern, forming spacers of the polymer at both sidewalls of the photoresist pattern, forming a second etching process using the spacers as a mask, to expose the oxide film, and removing the BARC, the photoresist pattern and the spacers by ashing and stripping.

Abstract: Embodiments relate to a flash memory device and a method of manufacturing a flash memory device that may improve a reliability of process by obtaining a Depth of Focus (DOF) in an exposure process. In embodiments, a method may include sequentially stacking an oxide film, a floating gate poly film, an ONO film, a control gate poly film, and a BARC (Bottom AntiReflect Coating) on a semiconductor substrate, forming a photoresist pattern for a stack gate on the BARC, and etching the BARC, the control gate poly film, the ONO film and the floating gate poly film at once by using the photoresist pattern until the oxide film is exposed.

Abstract: A semiconductor device can include a first interlayer dielectric layer disposed on a substrate, and an air gap defined in a portion of the first interlayer dielectric layer. The air gap can be formed within trenches etched into the first interlayer dielectric layer. An etch stop layer is disposed on the first interlayer dielectric layer and the air gap, and includes a hole communicating with the air gap.