Patents by Inventor Jeong-Yel Jang

Jeong-Yel Jang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7294908
    Abstract: A gate pattern having a critical dimension after an etching process of 60-70nm may be formed using an ArF photoresist as an etching mask by a method including sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a semiconductor wafer; forming a photoresist pattern by exposing and developing the ArF photoresist layer; etching the anti-reflection coating layer using the photoresist pattern as an etching mask; removing an oxide layer formed during etching of the anti-reflection coating layer; etching the gate electrode layer; and over-etching a remaining gate electrode layer.
    Type: Grant
    Filed: December 2, 2005
    Date of Patent: November 13, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventors: Jeong-Yel Jang, Sung-Ho Kwak
  • Publication number: 20070155170
    Abstract: There is provided a method of forming a damascene pattern including a via and a trench in a damascene process of forming a copper metal interconnection. The method includes forming an interlayer dielectric layer on a substrate, forming a first photosensitive layer pattern including a first opening that exposes a region in which a via is to be formed on the interlayer dielectric layer, etching the interlayer dielectric layer to a first depth using the first photosensitive layer pattern as an etching mask, removing the first photosensitive layer pattern and forming a second photosensitive layer pattern including a second opening that exposes a region in which a trench is to be formed on the interlayer dielectric layer, and etching the interlayer dielectric layer using the second photosensitive layer pattern as an etching mask to simultaneously form the via and the trench.
    Type: Application
    Filed: December 26, 2006
    Publication date: July 5, 2007
    Inventor: Jeong Yel Jang
  • Publication number: 20070154852
    Abstract: Embodiments relate to a method of patterning a thin film using a by-product of plasma. According to embodiments, the method may include (a) forming a thin film serving as a target object to be etched on a substrate, (b) forming photoresist patterns on the thin film, (c) performing a plasma treatment with respect to the photoresist pattern such that a by-product is attached to an outer wall of the photoresist pattern, and (d) patterning the thin film by using the photoresist patterns attached with the by-product as an etching mask. In embodiments, when a by-product of plasma is attached to a photoresist pattern such that the by-product of plasma is used as an etching mask, the thickness of the by-product may be formed as a desired thickness by controlling process variables.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 5, 2007
    Inventor: Jeong Yel Jang
  • Publication number: 20060128084
    Abstract: A gate pattern having a critical dimension after an etching process of 60-70 nm may be formed using an ArF photoresist as an etching mask by a method including sequentially forming a gate oxide layer, a gate electrode layer, an anti-reflection coating layer, and an ArF photoresist layer on a semiconductor wafer; forming a photoresist pattern by exposing and developing the ArF photoresist layer; etching the anti-reflection coating layer using the photoresist pattern as an etching mask; removing an oxide layer formed during etching of the anti-reflection coating layer; etching the gate electrode layer; and over-etching a remaining gate electrode layer.
    Type: Application
    Filed: December 2, 2005
    Publication date: June 15, 2006
    Inventors: Jeong-Yel Jang, Sung-Ho Kwak