Abstract: A cathode for a lithium secondary battery includes a cathode current collector, and a cathode active material layer formed on the cathode current collector. The cathode active material layer includes cathode active material particles. The cathode active material particles include a lithium metal oxide particle containing nickel and having a mole fraction of cobalt of 0.02 or less among all elements except lithium and oxygen.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.

Abstract: A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

Abstract: The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers that are alternately stacked, a channel plug at least partially passing through the stack structure on a cell region, and a plurality of support structures at least partially passing through the stack structure on a contact region.

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

Abstract: A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.

Abstract: A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.

Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.

Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.

Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.