Patents by Inventor Jeong-Yun Lee

Jeong-Yun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11125811
    Abstract: Provided are a semiconductor device and a method of operating the same. A semiconductor includes a test circuit which comprises: a test transistor to be tested for time-dependent dielectric breakdown (TDDB) characteristics using a stress voltage; an input switch disposed between a voltage application node to which the stress voltage is applied and an input node which transmits the stress voltage to the test transistor; and a protection switch disposed between the input node and a ground node.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: September 21, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-Goo Lee, Dae Han Kim, Ji Yun Kim, Jin Yub Lee
  • Publication number: 20210280469
    Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Sang Hyun LEE, Jeong Yun LEE, Seung Ju PARK, Geum Jung SEONG, Young Mook OH, Seung Soo HONG
  • Patent number: 11103905
    Abstract: An electrode rolling apparatus according to an embodiment of the present disclosure includes a sensing unit positioned above an electrode for a secondary battery being transferred along a lengthwise direction to measure a distance to the electrode for each location along a widthwise direction of the electrode, a control unit which identifies a location of a non-coated portion formed on the electrode using information associated with the distance between the sensing unit and the electrode measured through the sensing unit, and outputs a control signal to heat a region in which the identified non-coated portion is formed, a heating unit positioned above the electrode to selectively heat only the region in which the non-coated portion is formed according to the control signal of the control unit, and a rolling unit which rolls the electrode having the selectively heated region in which the non-coated portion is formed.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: August 31, 2021
    Inventors: Su-Yeon Yoo, Hye-Jin Song, In-Ae Yun, Jeong-Woo Lee, Kyu-Sung Jung, Hyo-Seung Jung, Min-Ji Heo
  • Patent number: 11037829
    Abstract: A semiconductor device capable of improving operation performance and reliability, may include a gate insulating support to isolate gate electrodes that are adjacent in a length direction.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: June 15, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang Hyun Lee, Jeong Yun Lee, Seung Ju Park, Geum Jung Seong, Young Mook Oh, Seung Soo Hong
  • Publication number: 20210159246
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Application
    Filed: January 8, 2021
    Publication date: May 27, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward CHO, Seok Hoon KIM, Myung Il KANG, Geo Myung SHIN, Seung Hun LEE, Jeong Yun LEE, Min Hee CHOI, Jeong Min CHOI
  • Patent number: 11011516
    Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: May 18, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-han Lee, Sun-ghil Lee, Myung-il Kang, Jeong-yun Lee, Seung-hun Lee, Hyun-jung Lee, Sun-wook Kim
  • Publication number: 20210098577
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Application
    Filed: December 11, 2020
    Publication date: April 1, 2021
    Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
  • Publication number: 20210090994
    Abstract: There are provided a semiconductor device and a manufacturing method thereof. The semiconductor device includes: a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers, which are stacked in an alternating manner; at least one support structure penetrating the stack structure in a substantially vertical manner, the at least one support structure being formed in a contact region; and a contact plug penetrating the stack structure in a substantially vertical manner, the contact plug being formed in the contact region, the contact plug being connected to a contact pad that is disposed on the bottom of the stack structure. The at least one support structure is formed of an oxide layer.
    Type: Application
    Filed: May 1, 2020
    Publication date: March 25, 2021
    Applicant: SK hynix Inc.
    Inventors: Jae Yoon NOH, Tae Kyung KIM, Hyo Sub YEOM, Jeong Yun LEE
  • Patent number: 10930668
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: February 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward Cho, Seok Hoon Kim, Myung Ii Kang, Geo Myung Shin, Seung Hun Lee, Jeong Yun Lee, Min Hee Choi, Jeong Min Choi
  • Patent number: 10896957
    Abstract: A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 19, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Namkyu Edward Cho, Seung Soo Hong, Geum Jung Seong, Seung Hun Lee, Jeong Yun Lee
  • Patent number: 10847416
    Abstract: A semiconductor device with improved product reliability and a method of fabricating the semiconductor are provided. The semiconductor device includes a substrate, a gate electrode on the substrate, a first spacer on a sidewall of the gate electrode, a conductive contact on a sidewall of the first spacer to protrude beyond a top surface of the gate electrode, a trench defined by the top surface of the gate electrode, a top surface of the first spacer, and sidewalls of the contact, an etching stop layer extending along at least parts of sidewalls of the trench and a bottom surface of the trench, and a capping pattern on the etching stop layer to fill the trench, wherein the capping pattern includes silicon oxide or a low-k material having a lower permittivity than silicon oxide.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Keun Hee Bai, Sung Woo Kang, Kee Sang Kwon, Dong Seok Lee, Sang Hyun Lee, Jeong Yun Lee, Yong-Ho Jeon
  • Patent number: 10840139
    Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a field insulating layer on the substrate, the field insulating layer wrapping a side wall of the fin type pattern, a gate electrode on the fin type pattern, the gate electrode extending in a second direction intersecting with the first direction, a first spacer on a side wall of a lower part of the gate electrode, and an etching stop layer extending along a side wall and an upper surface of an upper part of the gate electrode, along a side wall of the first spacer, and along an upper surface of the field insulating layer.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Geum Jung Seong, Seung Soo Hong, Young Mook Oh, Jeong Yun Lee
  • Publication number: 20200328207
    Abstract: A semiconductor device including a plurality of active regions extending in a first direction on a substrate; a device isolation layer between the plurality of active regions such that upper portions of the plurality of active regions protrude from the device isolation layer; a first gate electrode and a second gate electrode extending in a second direction crossing the first direction and intersecting the plurality of active regions, respectively, on the substrate, the first gate electrode being spaced apart from the second gate electrode in the second direction; a first gate separation layer between the first gate electrode and the second gate electrode; and a second gate separation layer under the first gate separation layer and between the first gate electrode and the second gate electrode, the second gate separation layer extending into the device isolation layer in a third direction crossing the first direction and the second direction.
    Type: Application
    Filed: January 10, 2020
    Publication date: October 15, 2020
    Inventors: Seung Soo HONG, Jeong Yun LEE, Geum Jung SEONG, Jin Won LEE, Hyun Ho JUNG
  • Patent number: 10714618
    Abstract: A semiconductor device includes a substrate having a fin active region pattern having a protruding shape, a device isolation layer pattern covering a side surface of a lower portion of the fin active region pattern, a spacer pattern covering a side surface of a portion of the fin active region pattern that protrudes from a top surface of the device isolation layer pattern, and a source/drain region in contact with a top surface of the fin active region pattern and a top surface of the spacer pattern.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Geum-jung Seong, Bo-ra Lim, Jeong-yun Lee, Ah-reum Ji
  • Publication number: 20200111784
    Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.
    Type: Application
    Filed: December 6, 2019
    Publication date: April 9, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jung-han LEE, Sun-ghil LEE, Myung-il KANG, Jeong-yun LEE, Seung-hun LEE, Hyun-jung LEE, Sun-wook KIM
  • Patent number: 10559565
    Abstract: An integrated circuit (IC) device includes a first and a second fin-type active region protruding from a first region and a second region, respectively, of a substrate, a first and a second gate line, and a first and a second source/drain region. The first fin-type active region has a first top surface and a first recess has a first depth from the first top surface. The first source/drain region fills the first recess and has a first width. The second fin-type active region has a second top surface and a second recess has a second depth from the second top surface. The second depth is greater than the first depth. The second source/drain region fills the second recess and has a second width. The second width is greater than the first width.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: February 11, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-han Lee, Sun-ghil Lee, Myung-il Kang, Jeong-yun Lee, Seung-hun Lee, Hyun-jung Lee, Sun-wook Kim
  • Publication number: 20200027895
    Abstract: A semiconductor device includes an active fin on a substrate, a gate electrode and intersecting the active fin, gate spacer layers on both side walls of the gate electrode, and a source/drain region in a recess region of the active fin at at least one side of the gate electrode. The source/drain region may include a base layer in contact with the active fin, and having an inner end and an outer end opposing each other in the first direction on an inner sidewall of the recess region. The source/drain region may include a first layer on the base layer. The first layer may include germanium (Ge) having a concentration higher than a concentration of germanium (Ge) included in the base layer. The outer end of the base layer may contact the first layer, and may have a shape convex toward outside of the gate electrode on a plane.
    Type: Application
    Filed: February 11, 2019
    Publication date: January 23, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Namkyu Edward CHO, Seok Hoon KIM, Myung II KANG, Geo Myung SHIN, Seung Hun LEE, Jeong Yun LEE, Min Hee CHOI, Jeong Min CHOI
  • Patent number: 10522616
    Abstract: A semiconductor device includes: a fin-type active region protruding from a substrate and extending in a first direction; at least one nano-sheet spaced apart from an upper surface of the fin-type active region and facing the upper surface of the fin-type active region, the at least one nano-sheet having a channel region; a gate extending on the fin-type active region in a second direction crossing the first direction and surrounding at least a portion of the at least one nano-sheet; a source/drain region on the fin-type active region on both sides of the at least one nano-sheet; and a source/drain protection layer on a sidewall of the at least one nano-sheet and between the source/drain region and the at least one nano-sheet.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: December 31, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Edward Nam-kyu Cho, Tae-soon Kwon, Bo-ra Lim, Jeong-yun Lee
  • Publication number: 20190348414
    Abstract: A semiconductor device has active fins defined by an isolation pattern on a substrate, each of the active fins extending in a first direction, and the active fins being spaced apart from each other in a second direction crossing the first direction, a gate electrode extending in the second direction on the active fins and the isolation pattern, and an isolation structure on a portion of the isolation pattern between the active fins neighboring with each other in the second direction. The isolation structure includes a first pattern having a first material and a second pattern having a second material different from the first material. The second pattern covers a lower surface and a lower side surface of the first pattern but not an upper side surface of the first pattern.
    Type: Application
    Filed: December 11, 2018
    Publication date: November 14, 2019
    Inventors: Seung-Soo HONG, Bo-Ra LIM, Geum-Jung SEONG, Young-Mook OH, Jeong-Yun LEE, Ah-Reum JI
  • Patent number: 10468994
    Abstract: An inverter for driving a motor of a vehicle mediating between a battery and a driving motor is disclosed. The inverter includes a power storage module, a power module, and a cooling module. The power storage module is configured to be supplied with power from the battery. The power module is configured to be supplied with power from the power storage module to transfer the power to the driving motor. The cooling module is configured to be installed between the power storage module and the power module to simultaneously cool the power storage module and the power module.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: November 5, 2019
    Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Ho Tae Chun, Se Min Woo, Chang Han Jung, Yun Ho Kim, Jeong Yun Lee, Seung Hyun Han