Abstract: A capacitor module of an inverter for a vehicle includes: a DC-link capacitor configured to be connected in parallel to an input of an inverter between a first high voltage input terminal and a second high voltage input terminal; and a plurality of Y-capacitors configured to be connected in parallel to the inverter. Each of the plurality Y-capacitors includes a first capacitor element connected between the first high voltage input terminal and a ground bus bar and a second capacitor element connected between the second high voltage input terminal and the ground bus bar, and the ground bus bars of the plurality of Y-capacitors are separately provided and the ground holes of the ground bus bars are disposed so as to face each other in a first direction.

Abstract: A method for changing a capacitance value of an output capacitor of a power factor corrector (PFC) includes applying AC power to a power conversion circuit. It is sensed whether an instantaneous power failure occurs in the AC power. Output capacitors of the PFC of the power conversion circuit are connected in parallel to each other to increase capacitance values of the output capacitors, when it is sensed that the instantaneous power failure does not occur in the AC power.

Abstract: An LCD device includes a first substrate including a display region having pixel regions and a non-display region disposed outside the display region; gate lines and data lines on the first substrate and cross each other to define the pixel regions; a TFT in each of the pixel regions; a pixel electrode in each pixel region and connected to the TFT; a second substrate disposed opposite the first substrate; a color filter layer on the second substrate; a common electrode; a liquid crystal layer between the first and second substrates; and an FPC connected to the non-display region on one side of the first substrate, the FPC being bent toward an outer side surface of the second substrate, wherein each of the gate lines has a double structure including a first layer of a transparent conductive material and a second layer of Cu or Cu alloy.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

Abstract: Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.

Abstract: Integrated circuit devices with source/drain regions including multiple segments and methods of forming the same are provided. The integrated circuit devices may include a gate structure on a substrate and a source/drain region in the substrate adjacent the gate structure. The source/drain region may include a sidewall including a plurality of curved sidewall sections.

Abstract: A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.

Abstract: Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.

Abstract: A DC-DC converter device and a sub DC-DC converter unit with parallel structure included in the same are disclosed. The DC-DC converter device includes a main DC-DC converter unit configured to receive a (1-1)th reference voltage, a (1-2)th reference voltage and a (n-1)th output voltage, and output an nth first output current corresponding to an nth output voltage; and a sub DC-DC converter unit configured to receive a second reference voltage and the (n-1)th output voltage, and output an nth second output current corresponding to the nth output voltage. Here, an output current in accordance with the nth output voltage corresponds to sum of the nth first output current and the nth second output current.

Abstract: A capacitor module of an inverter for a vehicle includes: a DC-link capacitor configured to be connected in parallel to an input of an inverter between a first high voltage input terminal and a second high voltage input terminal; and a plurality of Y-capacitors configured to be connected in parallel to the inverter. Each of the plurality Y-capacitors includes a first capacitor element connected between the first high voltage input terminal and a ground bus bar and a second capacitor element connected between the second high voltage input terminal and the ground bus bar, and the ground bus bars of the plurality of Y-capacitors are separately provided and the ground holes of the ground bus bars are disposed so as to face each other in a first direction.

Abstract: A method of forming a semiconductor device includes forming a gate structure including a polysilicon gate and forming a capping spacer on a side surface of the gate structure to prevent parasitic epitaxial growth on the side surface of the polysilicon gate.

Abstract: A semiconductor device includes a semiconductor substrate having a capacitor region and a resistor region. A capacitor dielectric material and a capacitor electrode are sequentially stacked on an active region in the capacitor region of the semiconductor substrate. A resistor is provided on the resistor region of the semiconductor substrate. A protection pattern is provided on a top surface of the capacitor electrode. The protection pattern is spaced apart from the capacitor electrode. The protection pattern and the resistor include the same material and have the same thickness in a direction vertical to a surface of the semiconductor substrate.

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.

Abstract: Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth.

Abstract: A semiconductor device includes a first multi-channel active pattern defined by a field insulating layer and extending along a first direction, the first multi-channel active pattern including a first portion having a top surface protruding further in an upward direction than a top surface of the field insulating layer and a second portion on both sides of the first portion, the second portion having sidewalls with a continuous profile and a top surface protruding further in the upward direction than the top surface of the field insulating layer and protruding in the upward direction less than the top surface of the first portion, a gate electrode on the first portion of the first multi-channel active pattern and extending along a second direction different from the first direction, and a first source/drain region on the second portion of the first multi-channel active pattern and contacting the field insulating layer.

Abstract: Provided are a semiconductor device and a method of fabricating a semiconductor device. The semiconductor device includes a first active fin and a second active fin which protrude from a substrate and extend along a first direction, a first gate structure which is on the first active fin to extend along a second direction intersecting the first direction, a second gate structure which is located adjacent to the first gate structure in the second direction and is on the second active fin to extend along the second direction, and a dummy structure which is in a space between the first gate structure and the second gate structure.

Abstract: A method of operating a plasma processing device includes outputting a first RF power having a first frequency and a first duty ratio, and outputting a second RF power having a second frequency higher than the first frequency and a second duty ratio smaller than the first duty ratio. The outputting of the first RF power and the outputting of the second RF power are synchronized with each other.

Abstract: Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.

Abstract: Integrated circuit devices with source/drain regions including multiple segments and methods of forming the same are provided. The integrated circuit devices may include a gate structure on a substrate and a source/drain region in the substrate adjacent the gate structure. The source/drain region may include a sidewall including a plurality of curved sidewall sections.

Abstract: An apparatus for an etching process includes a chamber, a plasma generator disposed in the chamber, a stacked structure disposed in the chamber to support a substrate thereon and including an electrode plate and an insulation coating layer on the electrode plate, electrode rods inserted into through holes of the stacked structure to penetrate through the stacked structure, directly contacting the substrate and spaced apart from sidewalls of the through holes of the stacked structure, at least one DC pulse generator generating a DC pulse to the electrode plate and the electrode rods, first connection lines connecting the DC pulse generator to the electrode rods, and at least one second connection line connecting the DC pulse generator to a lower portion of the electrode plate.