Abstract: One embodiment of the present disclosure provides an electrolytic copper foil includes a copper layer and has a width direction weight deviation of 5% or less calculated according to Equation 1 below, a tensile strength of 25 kgf/mm2 to 62 kgf/mm2, and a valley depth-to-thickness (VDT) of 3.5 to 66.9 calculated according to Equation 2 below. width direction weight deviation (%)=(standard deviation of weight/arithmetic mean of weight)×100, and??[Equation 1] VDT=[thickness of electrolytic copper foil]/[maximum valley depth of roughness profile(Rv)].

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a plurality of gate electrodes that are stacked on a substrate and are spaced apart from each other in a vertical direction and a channel region extending through the plurality of gate electrodes in the vertical direction. Each of the plurality of gate electrodes may include a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer. A first concentration of impurities in the second conductive layer may be higher than a second concentration of the impurities in the first conductive layer, and the impurities may include nitrogen (N).

Abstract: Disclosed is a copper foil including a copper layer and having a tensile strength of 29 to 65 kgf/mm2, a mean width of roughness profile elements (Rsm) of 18 to 148 ?m and a texture coefficient bias [TCB(220)] of 0.52 or less.

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

Abstract: A method of manufacturing a semiconductor device includes alternately stacking sacrificial layers and interlayer insulating layers on a substrate, to form a stack structure; forming channels penetrating through the stack structure; forming separation regions penetrating through the stack structure; forming lateral openings by removing the sacrificial layers through the separation regions; and forming gate electrodes in the lateral openings. Forming the gate electrodes may include forming a nucleation layer in the lateral openings by supplying a source gas and a first reaction gas, and forming a bulk layer on the nucleation layer to fill the lateral openings by supplying the source gas and a second reaction gas, different from the first reaction gas. The first reaction gas may be supplied from a first reaction gas source, stored in a gas charging unit, and supplied from the gas charging unit.

Abstract: An electrolytic copper foil for a lithium secondary battery, which is applied as a negative electrode current collector of a lithium secondary battery, wherein when a correlation between a thermal treatment temperature of the electrolytic copper foil for a lithium secondary battery, which corresponds to a variable x, and an elongation increment ratio of the electrolytic copper foil for a lithium secondary battery, which corresponds to a variable y, is expressed as y=ax+b (100?x?200) on an x-y two-dimensional graph, the “a” value is in the range of 0.0009 to 0.0610.

Abstract: An electrolytic copper foil for a lithium secondary battery, which is applied as a negative electrode current collector of a lithium secondary battery, wherein after a thermal treatment at 300° C. for 30 minutes, the electrolytic copper foil for a lithium secondary battery has an elongation of 5% to 30%.

Abstract: A high strength electrolytic copper foil preventing generation of folds, wrinkles, pleats, and breaks during a roll-to-roll (RTR) process, a method of manufacturing the same, and an electrode and a secondary battery which allow high productivity to be secured by being manufactured with such an electrolytic copper foil. The electrolytic copper foil includes a copper film including 99 weight % or more of copper and a protective layer on the copper film, wherein the electrolytic copper foil has a tensile strength of 45 to 65 kgf/mm2.

Abstract: A method of manufacturing a semiconductor device includes alternately stacking sacrificial layers and interlayer insulating layers on a substrate, to form a stack structure; forming channels penetrating through the stack structure; forming separation regions penetrating through the stack structure; forming lateral openings by removing the sacrificial layers through the separation regions; and forming gate electrodes in the lateral openings. Forming the gate electrodes may include forming a nucleation layer in the lateral openings by supplying a source gas and a first reaction gas, and forming a bulk layer on the nucleation layer to fill the lateral openings by supplying the source gas and a second reaction gas, different from the first reaction gas. The first reaction gas may be supplied from a first reaction gas source, stored in a gas charging unit, and supplied from the gas charging unit.

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a plurality of gate electrodes that are stacked on a substrate and are spaced apart from each other in a vertical direction and a channel region extending through the plurality of gate electrodes in the vertical direction. Each of the plurality of gate electrodes may include a first conductive layer defining a recess recessed toward the channel region, and a second conductive layer in the recess defined by the first conductive layer. A first concentration of impurities in the second conductive layer may be higher than a second concentration of the impurities in the first conductive layer, and the impurities may include nitrogen (N).

Abstract: A high strength electrolytic copper foil preventing generation of folds, wrinkles, pleats, and breaks during a roll-to-roll (RTR) process, a method of manufacturing the same, and an electrode and a secondary battery which allow high productivity to be secured by being manufactured with such an electrolytic copper foil. The electrolytic copper foil includes a copper film including 99 weight % or more of copper and a protective layer on the copper film, wherein the electrolytic copper foil has a tensile strength of 45 to 65 kgf/mm2.

Abstract: Disclosed is a copper foil including a copper layer and having a tensile strength of 29 to 65 kgf/mm2, a mean width of roughness profile elements (Rsm) of 18 to 148 ?m and a texture coefficient bias [TCB(220)] of 0.52 or less.

Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.

Abstract: An electrolytic copper foil for a lithium secondary battery, which is applied as a negative electrode current collector of a lithium secondary battery, wherein when a correlation between a thermal treatment temperature of the electrolytic copper foil for a lithium secondary battery, which corresponds to a variable x, and an elongation increment ratio of the electrolytic copper foil for a lithium secondary battery, which corresponds to a variable y, is expressed as y=ax+b (100?x?200) on an x-y two-dimensional graph, the “a” value is in the range of 0.0009 to 0.0610.

Abstract: A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

Abstract: A memory device may include a gate structure including a plurality of gate electrode layers and a plurality of insulating layers alternately stacked on a substrate, a plurality of etching stop layers, extending from the insulating layers respectively, being on respective lower portions of the gate electrode layers; and a plurality of contacts connected to the gate electrode layers above upper portions of the etching stop layers, respectively, wherein respective ones of the etching stop layers include an air gap therein.

Abstract: An electrolytic copper foil for a lithium secondary battery, which is applied as a negative electrode current collector of a lithium secondary battery, wherein after a thermal treatment at 300° C. for 30 minutes, the electrolytic copper foil for a lithium secondary battery has an elongation of 5% to 30%.

Abstract: A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.

Abstract: A memory device includes a gate structure, a contact plug, and a spacer. The gate structure includes first and second conductive layer patterns sequentially stacked on a substrate. The contact plug passes through the second conductive layer pattern, and a sidewall of the contact plug directly contacts at least a portion of the second conductive layer pattern. The spacer surrounds a portion of the sidewall of the contact plug and contacting the gate structure.

Abstract: A method and an apparatus for reducing Digital-to-Analog Conversion (DAC) bits at a transmitter of a Frequency Division Multiple Access (FDMA) system reduces a number of the bits for conversion so as to save power and reduce the cost of operation. The method can include generating a digital signal gain control value and an analog signal gain control value using subcarrier allocation information, a required Signal to Noise Ratio (SNR), and a Peak to Average Power Ratio (PAPR); controlling a gain of a signal input to a digital-to-analog converter using the digital signal gain control value; converting a digital signal of the controlled gain to an analog signal using the digital-to-analog converter; and restoring an original signal by controlling a gain of a signal output from the digital-to-analog converter using the analog signal gain control value.