Abstract: A semiconductor memory apparatus is configured to perform a mismatch compensation operation of a bitline sense amplifier and enable a wordline electrically coupled with a bitline, after electrically isolating an input node of the bitline sense amplifier and the bitline. When the mismatch compensation operation of the bitline sense amplifier is completed, the semiconductor memory apparatus is configured to electrically couple the bitline and the input node of the bitline sense amplifier to develop a voltage level difference between the bitline and a bitline bar.

Abstract: Disclosed herein are an apparatus and method for accelerating sludge granulation. The apparatus for accelerating sludge granulation, which serves to accelerate a process of granulating activated sludge to produce granules, includes a cultivation tank configured to receive activated sludge and a carbon source to culture them in a preset environment for a preset time, an acceleration reactor configured to receive the activated sludge cultured in the cultivation tank and sewage from the outside to grow and granulate the activated sludge, and a control unit configured to control operations of the cultivation tank and the acceleration reactor.

Abstract: An operation method of memory may include activating a first row that is selected in a first bank, activating a second row that is selected in a second bank, receiving an all-bank counting command, reading a first access count from memory cells of specific columns of the first row in response to the all-bank counting command, increasing the first access count, writing the increased first access count in the memory cells of the specific columns of the first row, reading a second access count from memory cells of specific columns of the second row in response to the all-bank counting command, increasing the second access count, and writing the increased second access count in the memory cells of the specific columns of the second row.

Abstract: An operation method of memory may include activating a first row that is selected in a first bank, activating a second row that is selected in a second bank, receiving an all-bank counting command, reading a first access count from memory cells of specific columns of the first row in response to the all-bank counting command, increasing the first access count, writing the increased first access count in the memory cells of the specific columns of the first row, reading a second access count from memory cells of specific columns of the second row in response to the all-bank counting command, increasing the second access count, and writing the increased second access count in the memory cells of the specific columns of the second row.

Abstract: A method of forming a thin film using a substrate processing apparatus includes placing the substrate on the electrostatic chuck, depositing the thin film on the substrate, transferring the substrate, and performing a hardening process. The depositing the thin film on the substrate applies a first DC power source to chuck the substrate, supplies a process gas and applies a first RF power source to form a first plasma to deposit the thin film on the substrate. The transferring the substrate transfers the substrate on which the thin film has been deposited outside the process chamber. The performing a hardening process applies a second DC power source, supplies a purge gas, and applies a second RF power source to form the plasma to harden a deposition film formed in an interior of the process chamber.

Abstract: There is provided a method of executing a multiplication and accumulation (MAC) calculation in a PIM device. The method may include outputting first data and a parity from a first storage region, outputting second data from a second storage region, simultaneously executing an error correction code (ECC) calculation of the first data and the parity and a multiplying calculation of the first and second data, generating an error code indicating an error location of the first data as a result of the ECC calculation, outputting multiplication result data corresponding to a result of the multiplying calculation when no error exists in the first data based on the error code, and executing a compensating calculation of the multiplication result data to output the compensated multiplication result data when an error exists in the first data based on the error code.

Abstract: A method for operating a memory includes: receiving a first write command and a first write address; receiving first write data a portion of which is masked; reading first read data and a first read error correction code from a region selected based on the first write address in a cell array; detecting and correcting an error in the first read data based on the first read error correction code to produce error-corrected first read data; generating first new write data by replacing the masked portion of the first write data with a portion of the error-corrected first read data; generating a first write error correction code based on the first new write data; and writing the first new write data and the first write error correction code into the region selected based on the first write address in response to the detecting of the error.

Abstract: A Processing-In-Memory (PIM) device includes a first storage region and a multiplication/accumulation (MAC) calculator. The first storage region configured to store a first data. The MAC operator configured to execute a MAC calculation on the first data and second data in an MAC mode. When an error exists in the first data, the MAC operator compensates multiplication result data generated by a multiplying calculation of the first data and the second data and executes an adding calculation of the compensated multiplication result data.

Abstract: A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Abstract: An apparatus includes a potential failure information generation circuit configured to generate potential failure inforrnation by detecting, based on first failure information on a first faded signal line and second failure information on a second faded signal line, whether the first failed signal line and the second faded signal line are adjacent to each other; and a flag generation circuit configured to generate a flag by comparing the potential failure information with redundancy repair information.

Abstract: A method of performing a MAC arithmetic operation includes detecting error correction capability for first data when a command has a logic level combination for performing the MAC arithmetic operation; correcting an error, included in the first data, when the number of erroneous bits included in the first data is equal to or less than the error correction capability; and outputting, to a PIM controller, MAC calculation result data generated by performing the MAC arithmetic operation on the error-corrected first data.

Abstract: A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.

Abstract: A Processing-In-Memory (PIM) device includes an error correction code (ECC) logic circuit and an error accumulation detection circuit. The error correction code (ECC) logic circuit configured to detect an erroneous bits included in first data to generate a parity bit, and to detect an error correction capability of the first data to generate an error correction fail signal. The error accumulation detection circuit configured to generate an error accumulation signal counted by a pulse of the error correction fail signal. The error correction capability set to the maximum number of erroneous bits that can be corrected by performing an ECC operation on the first data.

Abstract: A method for operating a memory includes: receiving a first write command and a first write address; receiving first write data a portion of which is masked; reading first read data and a first read error correction code from a region selected based on the first write address in a cell array; detecting and correcting an error in the first read data based on the first read error correction code to produce error-corrected first read data; generating first new write data by replacing the masked portion of the first write data with a portion of the error-corrected first read data; generating a first write error correction code based on the first new write data; and writing the first new write data and the first write error correction code into the region selected based on the first write address in response to the detecting of the error.

Abstract: A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.

Abstract: An electronic device includes a core circuit configured to store write data and a write parity after outputting read data and a read parity in a data masking operation. The electronic device also includes an error correction circuit configured to correct an error included in the read data, based on the read parity; generate the write parity from the error-corrected read data, input data, and masking data; and generate the write data from the error-uncorrected read data, the input data, and the masking data.

Abstract: A latch circuit includes a plurality of latch sets, each including an enable latch and a plurality of address latches; and a plurality of latch-width adjusting circuits respectively corresponding to the latch sets, wherein, in each of the plurality of latch sets, the corresponding latch-width adjusting circuit is disposed between the enable latch of the corresponding latch set and the address latch adjacent to the enable latch, and couples the enable latch to the adjacent address latch depending on whether or not the corresponding latch set is used, at an end of a boot-up operation.

Abstract: An apparatus includes a potential failure information generation circuit configured to generate potential failure inforrnation by detecting, based on first failure information on a first faded signal line and second failure information on a second faded signal line, whether the first failed signal line and the second faded signal line are adjacent to each other; and a flag generation circuit configured to generate a flag by comparing the potential failure information with redundancy repair information.

Abstract: An electronic device includes a core circuit configured to store write data and a write parity after outputting read data and a read parity in a data masking operation. The electronic device also includes an error correction circuit configured to correct an error included in the read data, based on the read parity; generate the write parity from the error-corrected read data, input data, and masking data; and generate the write data from the error-uncorrected read data, the input data, and the masking data.

Abstract: Disclosed is a neuron circuit in which an overflow signal before fire is retained after the fire. The neuron circuit according to an embodiment of the inventive concept includes a synapse element, a synaptic integration unit and a pulse generation unit. The synapse element receives output signals of a pre-neuron circuit and a post-neuron circuit. The synaptic integration unit includes a capacitor charged by the current flowing into the synapse element depending on the output signals of the pre-neuron circuit and the post-neuron circuit. The pulse generation unit generates an output pulse from the charging voltage of the capacitor.