Abstract: A cooling structure includes a housing having a cooling channel defined therein through which a coolant flows and includes a sealing cap fitted to a hole of the housing to seal the hole. The sealing cap includes a blocking member configured to be in contact with an internal surface of the housing. The cooling structure may be for cooling a motor, such as an in-wheel vehicle motor.

Abstract: A display device and a method of fabricating a display device are provided. The display device includes a substrate comprising a contact area and a line area, a first electrode that extends in a first direction on the substrate, a first electrode pattern that extends in the first direction and is spaced apart from the first electrode on the substrate, a second electrode that extends in the first direction and is between the first electrode and the first electrode pattern on the substrate, a second electrode pattern that extends in the first direction and is between the first electrode and the second electrode on the substrate, and a first light-emitting element between the first electrode and the second electrode pattern in the contact area.

Abstract: A channel structure includes a cooling channel continuously formed inside a housing. A coolant is configured to flow in the cooling channel. The cooling channel includes a plurality of channel portions spaced apart from each other and extending in the housing by changing directions.

Abstract: Disclosed are a binder for a secondary battery anode including styrene-butadiene-based rubber with a core-shell structure and nitrile-butadiene-based rubber with a gel content of 15% or more, wherein a weight ratio of the styrene-butadiene-based rubber and the nitrile-butadiene-based rubber is 65:35 to 99:1, an anode mixture for a secondary battery, and an anode and a secondary battery including the same.

Abstract: The present disclosure provides a sealing device and an in-wheel motor including the sealing device. The in-wheel motor includes a stator, a rotor rotatably disposed with respect to the stator, an annular inner seal connected to the stator and spaced apart from the rotor by a predetermined gap so as to be disposed between the stator and the rotor, and an annular slinger coupled to an end portion of the rotor, wherein the annular inner seal seals between the slinger and the in-wheel motor.

Abstract: The present disclosure provides a basal ganglia-on-a-chip for screening therapeutic agents for brain and nervous system diseases and a method for fabricating the same. The present invention provides a method for screening therapeutic agents for dopamine-dependent brain and nervous system diseases by using a basal ganglia-on-a-chip. When the basal ganglia-on-a-chip of the present invention is used in the effect evaluation of therapeutic agents for brain and nervous system diseases, the effect evaluation of therapeutic candidate substances can be economically and promptly carried out compared with an existing technique.

Abstract: A semiconductor device including: a first transistor which include a first gate stack on a substrate; and a second transistor which includes a second gate stack on the substrate, wherein the first gate stack includes a first ferroelectric material layer disposed on the substrate, a first work function layer disposed on the first ferroelectric material layer and a first upper gate electrode disposed on the first work function layer, wherein the second gate stack includes a second ferroelectric material layer disposed on the substrate, a second work function layer disposed on the second ferroelectric material layer and a second upper gate electrode disposed on the second work function layer, wherein the first work function layer includes the same material as the second work function layer, and wherein an effective work function of the first gate stack is different from an effective work function of the second gate stack.

Abstract: A method of automatically detecting a dynamic object recognition error in an autonomous vehicle is provided. The method includes parsing sensor data obtained by frame units from a sensor device equipped in an autonomous vehicle to generate raw data by using a parser, analyzing the raw data to output a dynamic object detection result by using a dynamic object recognition model, determining that detection of a dynamic object recognition error succeeds by using an error detector when the dynamic object detection result satisfies an error detection condition, and storing the raw data and the dynamic object detection result by using a non-volatile memory when the detection of the dynamic object recognition error succeeds.

Abstract: Disclosed are novel compounds of Chemical Formula 1, optical isomers of the compounds, and pharmaceutically acceptable salts of the compounds or the optical isomers. The compounds, isomers, and salts exhibit excellent activity as GLP-1 receptor agonists. In particular, they, as GLP-1 receptor agonists, exhibit excellent glucose tolerance, thus having a great potential to be used as therapeutic agents for metabolic diseases. Moreover, they exhibit excellent pharmacological safety for cardiovascular systems.

Abstract: Provided is a ceiling storage system capable of correcting a working position and constantly checking stability of a structure by detecting an amount of change in a facility. According to the ceiling storage system, a transport vehicle moves to an upper portion of a first storage area of a plurality of storage areas in a state of gripping an article, and the transport vehicle measures a first distance value between the transport vehicle and the first storage area using a distance sensor and measures a relative position value between the transport vehicle and the first storage area using a vision sensor, before unloading the article from the first storage area.

Abstract: There is provided a method of executing a multiplication and accumulation (MAC) calculation in a PIM device. The method may include outputting first data and a parity from a first storage region, outputting second data from a second storage region, simultaneously executing an error correction code (ECC) calculation of the first data and the parity and a multiplying calculation of the first and second data, generating an error code indicating an error location of the first data as a result of the ECC calculation, outputting multiplication result data corresponding to a result of the multiplying calculation when no error exists in the first data based on the error code, and executing a compensating calculation of the multiplication result data to output the compensated multiplication result data when an error exists in the first data based on the error code.

Abstract: A method for operating a memory includes: receiving a first write command and a first write address; receiving first write data a portion of which is masked; reading first read data and a first read error correction code from a region selected based on the first write address in a cell array; detecting and correcting an error in the first read data based on the first read error correction code to produce error-corrected first read data; generating first new write data by replacing the masked portion of the first write data with a portion of the error-corrected first read data; generating a first write error correction code based on the first new write data; and writing the first new write data and the first write error correction code into the region selected based on the first write address in response to the detecting of the error.

Abstract: A Processing-In-Memory (PIM) device includes a first storage region and a multiplication/accumulation (MAC) calculator. The first storage region configured to store a first data. The MAC operator configured to execute a MAC calculation on the first data and second data in an MAC mode. When an error exists in the first data, the MAC operator compensates multiplication result data generated by a multiplying calculation of the first data and the second data and executes an adding calculation of the compensated multiplication result data.

Abstract: A processing-in-memory (PIM) device includes a multiplication/accumulation (MAC) operator. The MAC operator includes a multiplying block and an adding block. The multiplying block includes a first multiplier and a second multiplier. The first multiplier performs a first multiplying calculation of first half data of first data and first half data of second data. The second multiplier performs a second multiplying calculation of second half data of the first data and second half data of the second data. The adding block performs an adding calculation of first multiplication result data outputted from the first multiplier and second multiplication result data outputted from the second multiplier. The MAC operator receives a test mode signal having a first level to perform a test operation for the multiplying block.

Abstract: An apparatus includes a potential failure information generation circuit configured to generate potential failure inforrnation by detecting, based on first failure information on a first faded signal line and second failure information on a second faded signal line, whether the first failed signal line and the second faded signal line are adjacent to each other; and a flag generation circuit configured to generate a flag by comparing the potential failure information with redundancy repair information.

Abstract: A method of performing a MAC arithmetic operation includes detecting error correction capability for first data when a command has a logic level combination for performing the MAC arithmetic operation; correcting an error, included in the first data, when the number of erroneous bits included in the first data is equal to or less than the error correction capability; and outputting, to a PIM controller, MAC calculation result data generated by performing the MAC arithmetic operation on the error-corrected first data.

Abstract: A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.

Abstract: A Processing-In-Memory (PIM) device includes an error correction code (ECC) logic circuit and an error accumulation detection circuit. The error correction code (ECC) logic circuit configured to detect an erroneous bits included in first data to generate a parity bit, and to detect an error correction capability of the first data to generate an error correction fail signal. The error accumulation detection circuit configured to generate an error accumulation signal counted by a pulse of the error correction fail signal. The error correction capability set to the maximum number of erroneous bits that can be corrected by performing an ECC operation on the first data.

Abstract: A method for operating a memory includes: receiving a first write command and a first write address; receiving first write data a portion of which is masked; reading first read data and a first read error correction code from a region selected based on the first write address in a cell array; detecting and correcting an error in the first read data based on the first read error correction code to produce error-corrected first read data; generating first new write data by replacing the masked portion of the first write data with a portion of the error-corrected first read data; generating a first write error correction code based on the first new write data; and writing the first new write data and the first write error correction code into the region selected based on the first write address in response to the detecting of the error.

Abstract: A Processing-In-Memory (PIM) device includes a MAC operator, a first storage region and an error correction code (ECC) logic circuit. The MAC operator performs MAC operation of first data and second data. The first storage region provides the first data to the MAC operator. The error correction code (ECC) logic circuit transmit first encoded data to the first storage region by performing a first ECC encoding operation on the first data. The error correction code (ECC) logic circuit transmit first decoded data generated by performing a first ECC decoding operation of the first encoded data transmitted from the first storage region to the MAC operator. The error correction code (ECC) logic circuit generates an error calculation result signal and transmit the an error calculation result signal to the MAC operator when the number of erroneous bits detected in the first ECC decoding operation exceed an error correction capability.