Abstract: A method of forming semiconductor device comprises the following steps. A first fin and a second fin are formed protruding from a substrate, wherein each of the first fin and the second fin comprises alternately stacked first nanostructures and second nanostructures. A dummy gate is formed cross the first fin and the second fin and extending along a direction. Sidewalls of the first nanostructures of the first fin and sidewalls of the first nanostructures of the second fin are etched to form sidewall recesses. A dielectric wall is formed between the first fin and the second fin, wherein the dielectric wall fills in the sidewall recesses. A first portion of the dummy gate is removed to form a gate trench exposing the first fin. The first nanostructures of the first fin in the gate trench are removed. Agate structure is formed in the gate trench.

Abstract: A memory device is provided. The memory device includes a write pass-gate transistor, a read pass-gate transistor, a write word line, and a read word line. The write pass-gate transistor is disposed in a first layer. The read pass-gate transistor is disposed in a second layer above the first layer. The write word line is disposed in a metallization layer above the first layer and electrically coupled to the write pass-gate transistor through a write path. The read word line is disposed in the metallization layer and electrically coupled to the read pass-gate transistor through a read path. The write path is different from the read path.

Abstract: A device includes a first gate structure, a second gate structure, a third gate structure and a first conductive segment. The first gate structure corresponds to a control terminal of a first switch. The second gate structure corresponds to a control terminal of a second switch. The third gate structure corresponds to a control terminal of a third switch, and coupled to the first gate structure. The first conductive segment is configured to couple the first switch, the second switch and the third switch to each other, and disposed between the second gate structure and the third gate structure. A distance between the first gate structure and the second gate structure is approximately equal to a distance between the third gate structure and the second gate structure.

Abstract: A semiconductor device and a logic device formed of the semiconductor device are provided. The semiconductor device includes a first field effect transistor (FET), disposed on a semiconductor substrate, and including vertically separated first channel structures formed as thin sheets each having opposite major planar surfaces facing toward and away from the semiconductor substrate; and a second FET, disposed on the semiconductor substrate and overlapped with the first FET. A conductive type of the second FET is complementary to a conductive type of the first FET. Second channel structures of the second FET are separately arranged along a lateral direction, and formed as thin walls.

Abstract: An electronic device and a method for manufacturing the same are provided. The electronic device includes a substrate and a gate structure. The substrate includes a fin. The fin includes a source region and a drain region spaced apart from the source region. The gate structure is located between the source region and the drain region. The gate structure includes a work function layer. The work function layer includes a compound of a metal material and a Group VIA material.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: A semiconductor device includes first and second transistors. The first transistor includes first semiconductor channel layers and a first gate structure. The first gate structure includes a first interfacial layer, a first high-k dielectric layer, and a first filling metal. A region of the first interfacial layer close to the first high-k dielectric layer has a higher concentration of a first metal element than a region of the first interfacial layer away from the first high-k dielectric layer. The second transistor includes second semiconductor channel layers and a second gate structure. The second gate structure includes a second interfacial layer, a second high-k dielectric layer, and a second filling metal. A region of the second high-k dielectric layer close to the second filling metal has a higher concentration of the first metal element than a region of the second high-k dielectric layer away from the second filling metal.

Abstract: Device structures and methods of forming the same are provided. A device structure according to the present disclosure includes a substrate having a front side and a back side, a fin structure over the front side, a plurality of nanostructures disposed over the fin structure, a gate structure wrapping around each of the plurality of nanostructures, a first doped region disposed over the back side of the substrate, a backside dielectric layer over the first doped region, and a first contact feature extending through the backside dielectric layer to interface the first doped region.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate and a transistor in the substrate. The transistor includes a gate structure penetrating through the substrate, a first source/drain region at a front side of the substrate, and a second source/drain region at a back side of the substrate.

Abstract: A semiconductor device and a logic device formed of the semiconductor device are provided. The semiconductor device includes a first field effect transistor (FET), disposed on a semiconductor substrate, and including vertically separated first channel structures formed as thin sheets each having opposite major planar surfaces facing toward and away from the semiconductor substrate; and a second FET, disposed on the semiconductor substrate and overlapped with the first FET. A conductive type of the second FET is complementary to a conductive type of the first FET. Second channel structures of the second FET are separately arranged along a lateral direction, and formed as thin walls.

Abstract: Memory devices and related methods are disclosed. A memory cell can include one or more first conduction channels extending along a first lateral direction, overlaid by a first gate structure and a parallel second gate structure, both extending along a second lateral direction. A second conduction channel can be disposed parallel to the first conduction channels. A third gate structure can overlay the second conduction channel. The device can further include a first interconnect structure extending along the second lateral direction, overlying both the first and second conduction channels, and a second interconnect structure extending along the second lateral direction and overlying only the first conduction channels.

Abstract: A memory device includes a transistor and a memory cell. The transistor includes a gate electrode disposed over a substrate and source/drain regions in the substrate beside the gate electrode. The memory cell is disposed over the transistor and includes a bottom electrode electrically connected to one of the source/drain regions, a top electrode disposed over the bottom electrode, and a first bit and a second bit separated from each other and disposed between the bottom electrode and the top electrode.

Abstract: A semiconductor device includes a substrate and a quantum dot transistor disposed on the substrate and includes a first barrier gate stack, a second barrier gate stack and a first plunger gate stack disposed between the first barrier gate stack and the second barrier gate stack. The first barrier gate stack and the first plunger gate stack are arranged in a first straight axis, the first plunger gate stack and the second barrier gate stack are arranged in a second straight axis, and there is a first angle between the first straight axis and the second straight axis is not equal to 180°.

Abstract: Qubits in a quantum computing semiconductor device may be arranged in a two-dimensional array. The two-dimensional array may be implemented using fin-based semiconductor manufacturing techniques. For example, a first active semiconductor region (e.g., a first fin structure) may extend in a first direction and a second active semiconductor region (e.g., a second fin structure) may extend in a second direction. A qubit may be located an intersection point between the first active semiconductor region and the second semiconductor region. This enables qubits to be formed in a grid in the two-dimensional array, which provides greater qubit density and shorter distances between qubits (and thus, greater quantum computing performance) compared to one-dimensional (e.g., linear) qubit arrays.

Abstract: A method includes forming first bonding pads over a first substrate, wherein the first bonding pads include a layer of ferromagnetic material, wherein each first bonding pad produces a respective magnetic field having a first orientation; and bonding second bonding pads to the first bonding pads using metal-to-metal bonding.

Abstract: The disclosure provides a memory device, a memory array, and an N-bit memory unit. The memory device includes a memory array including an N-bit memory unit, wherein N is a positive integer. The N-bit memory unit includes a first memory cell, used to characterize at least two first bits of a plurality of least significant bits of the N-bit memory unit.

Abstract: A memory device and a semiconductor die are provided. The memory device includes: a non-volatile storage device, with a first terminal coupled to a bit line; and an access transistor, configured to control electrical connection between a second terminal of the non-volatile storage device and a source line, and comprising an N-type field effect transistor (NFET) and a P-type field effect transistor (PFET) stacked on the NFET. A common source/drain terminal of the NFET and the PFET is coupled to the second terminal of the non-volatile storage device. Another common source/drain terminal of the NFET and the PFET is coupled to the source line. Further, gate terminals of the NFET and the PFET are coupled to different word lines.

Abstract: A method of making a semiconductor device includes forming a write transistor partially in a substrate. The method further includes forming an interconnect structure over the substrate. The method further includes forming a read transistor in the interconnect structure, wherein the read transistor is physically separated from the substrate. The method further includes forming at least one storage element electrically connected to each of the write transistor and the read transistor, wherein forming the at least one storage element comprises forming the at least one storage element between the write transistor and the read transistor in a direction perpendicular to a top surface of the substrate.

Abstract: Semiconductor structures and formation processes thereof are provided. A semiconductor structure of the present disclosure includes a semiconductor substrate, a plurality of transistors disposed on the semiconductor substrate and comprising a plurality of gate structures extending lengthwise along a first direction, a metallization layer disposed over the plurality of transistors, the metallization layer comprising a plurality of metal layers and a plurality of contact vias, a dielectric layer over the metallization layer, a plurality of dielectric fins extending parallel along the first direction and disposed over the dielectric layer, a semiconductor layer disposed conformally over the plurality of dielectric fins, a source contact and a drain contact disposed directly on the semiconductor layer, and a gate structure disposed over the semiconductor layer and between the source contact and the drain contact.

Abstract: A method of manufacturing an integrated circuit includes depositing a first dielectric layer having a thickness TD1. The method further includes patterning and etching the first dielectric layer to form a primary recess having a sidewall depth DR1, a recess width WR1, and a recess length LR1. The method further includes depositing a first conductive layer having a thickness TC1 in the primary recess, a residual portion of the primary recess forming a secondary recess. The method further includes depositing a second dielectric layer in the secondary recess. The method further includes planarizing the integrated circuit to form a planar surface with a residual portion of the first conductive layer forming a first conductive structure within the primary recess. The first conductive structure includes a horizontal portion and a vertical portion, and a first contact surface of the vertical portion is exposed on the planar surface.