Abstract: A memory array and a structure of the memory array are provided. The memory array includes flash transistors, word lines and bit lines. The flash transistors are arranged in columns and rows. The flash transistors in each column are in serial connection with one another. The word lines are respectively coupled to gate terminals of a row of the flash transistors. The bit lines are respectively coupled to opposite ends of a column of the flash transistors. Band-to-band tunneling current at a selected flash transistor is utilized as read current during a read operation. The BTB tunneling current flows from one of the source/drain terminals of the selected flash transistor to the substrate, rather than flowing from one of the source/drain terminals to the other. As a result, charges stored in multiple programming sites of each flash transistor can be respectively sensed.

Abstract: Provided are a memory cell and a method of forming the same. The memory cell includes a first dielectric pattern, a second dielectric pattern, a first bottom electrode, a first storage pattern, and a first top electrode. The first bottom electrode is disposed between the first dielectric pattern and the second dielectric pattern, and the first bottom electrode interfaces a first sidewall of the first dielectric pattern and a sidewall of the second dielectric pattern. The first storage pattern is disposed on the first dielectric pattern, the second dielectric pattern and the first bottom electrode, wherein the first storage pattern is electrically connected to the first bottom electrode. The first storage pattern is between the first bottom electrode and the first top electrode. A semiconductor die including a memory array is also provided.

Abstract: A method includes forming a first gate dielectric, a second gate dielectric, and a third gate dielectric over a first semiconductor region, a second semiconductor region, and a third semiconductor region, respectively. The method further includes depositing a first lanthanum-containing layer overlapping the first gate dielectric, and depositing a second lanthanum-containing layer overlapping the second gate dielectric. The second lanthanum-containing layer is thinner than the first lanthanum-containing layer. An anneal process is then performed to drive lanthanum in the first lanthanum-containing layer and the second lanthanum-containing layer into the first gate dielectric and the second gate dielectric, respectively. During the anneal process, the third gate dielectric is free from lanthanum-containing layers thereon.

Abstract: An anti-seismic device is adapted to absorb the vibration energy of a structure, and comprises a plurality of vibration-reducing units, each of which includes a mass, a hydraulic cylinder, and a resilient element. The hydraulic cylinder has an outer end that is connected fixedly to the structure, and an inner end that is connected fixedly to the mass. The resilient element has an outer end that is connected to the structure, and an inner end that is connected to the mass. When the structure is subjected to vibration, the masses can move reciprocally relative to the structure at different vibration frequencies. The hydraulic cylinders are arranged substantially in parallel.

Abstract: An anti-seismic device is adapted to absorb the vibration energy of a structure, and comprises a plurality of vibration-reducing units, each of which includes a mass, a hydraulic cylinder, and a resilient element. The hydraulic cylinder has an outer end that is connected fixedly to the structure, and an inner end that is connected fixedly to the mass. The resilient element has an outer end that is connected to the structure, and an inner end that is connected to the mass. When the structure is subjected to vibration, the masses can move reciprocally relative to the structure at different vibration frequencies. The hydraulic cylinders are arranged substantially in parallel.