Patents by Inventor Jer Lin

Jer Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040130266
    Abstract: A plasma display panel comprises a plurality of red, green and blue display units arranged on a substrate, so as to form plural red, green, blue display unit channels whose directions are aligned towards a ventilation hole located on the substrate, for facilitating gas charge or discharge in a good speed.
    Type: Application
    Filed: August 8, 2003
    Publication date: July 8, 2004
    Inventors: Yao-Ching Su, Chung-Kuang Tsai, Yih-Jer Lin
  • Publication number: 20040056175
    Abstract: A CMOS light sensor and the operation method thereof are disclosed. The CMOS light sensor has a plurality of light sensing lines and a plurality of capacitor lines. Each light sensing line has a plurality of light sensors such that the number of capacitors in each capacitor line is smaller than the number of light sensing cells in each light sensing line. The capacitors are used for holding a portion of the potentials produced by the light sensing cells due to illumination. The method of operating the CMOS light sensor includes transferring the data captured by the light sensing line to the capacitor line and reading out the data according to a pre-defined order so that the leakage of charges from the capacitor is reduced.
    Type: Application
    Filed: April 7, 2003
    Publication date: March 25, 2004
    Inventors: BEN. MIN-JER LIN, SHIH-HUANG CHEN
  • Patent number: 6621215
    Abstract: A front plate of a plasma display panel (PDP) comprising a glass substrate, a auxiliary electrode formed in the glass substrate, and a protecting electrode over the auxiliary electrode is disclosed. The auxiliary electrode is inlaid in the glass substrate or in a buffer layer formed atop the glass substrate. The protecting electrode is formed to prevent a bonding auxiliary electrode of the auxiliary electrode from being oxidized easily during a high temperature process. Another front plate of a PDP is disclosed and includes a glass substrate, a sustaining electrode on the glass substrate, an auxiliary electrode on the sustaining electrode, and a protecting electrode disposed on the auxiliary electrode. Again, the protecting electrode is formed to prevent the bonding auxiliary electrode of the auxiliary electrode from being oxidized easily during a high temperature process.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: September 16, 2003
    Assignee: AU Optronics Corp.
    Inventors: Yao Ching Su, Yih Jer Lin
  • Patent number: 6593988
    Abstract: A multi-domain liquid crystal display (LCD) has a plurality of wall-bump structures formed on a common electrode layer on a substrate. Each wall-bump structure consists of at least one wall-bump disposed in a pixel area. Wall-bumps of many different shapes can be used in the wall-bump structure. The wall-bump structure is manufactured by a standard photo-lithographic process. It provides pre-tilted angles for liquid crystal molecules and results in orderly alignment of liquid crystal molecules when an external voltage is applied. By means of the fringe field effect to tilt liquid crystal molecules, a multi-domain LCD cell can be established after a voltage is applied. The multi-domain LCD provides fast response speed for its application and higher transmittance than a conventional vertically aligned wide-viewing angle LCD.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: July 15, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Hong-Da Liu, Ing-Jer Lin, Ching-Her Chao, Dai-Liang Ting
  • Patent number: 6531776
    Abstract: A method of forming a semiconductor device having reduced interconnect-line parasitic capacitance is provided. The method includes the following steps. First, a substrate is provided and a plurality of interconnect lines are formed on the substrate. A barrier layer is then formed. Next, the barrier layer is hardened and thinned so as to make the barrier layer having a thin-film attribute. Following that, a separation layer is formed by filling the space between and above the interconnect lines with a dielectric. Then, the dielectric is foamed. After that, an insulating layer is formed. Finally, the dielectric is condensed such that air gaps are formed in the separation layer.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: March 11, 2003
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Ben Min-Jer Lin, Sheng-Jen Wang
  • Publication number: 20030011734
    Abstract: A multi-domain liquid crystal display has at least one wall bump structure formed on one of pixel and common electrode layers. Each wall bump structure has a plurality of boundaries and the opposite sides of the boundaries are not parallel to each other. One of the electrode layers may be formed with openings. The non-parallel boundaries of the wall bump structures cause various pre-tilted directions for the liquid crystals filling the gap between two substrates. The viewing angle of the liquid crystal display is increased and the stability of the multi-domain effect is enhanced with the wall bump structures. The liquid crystals may be aligned vertically, horizontally, tilted with an angle, or reverse tilted with an angle using a mask rubbing process or a photo aligned method. If wall bump structures are formed on both pixel and common electrode layers, they may overlap each other.
    Type: Application
    Filed: July 10, 2001
    Publication date: January 16, 2003
    Inventors: Hong-Da Liu, Ching-Yih Chen, Ing-Jer Lin, Ching-Her Chao
  • Patent number: 6507150
    Abstract: A front plate of a plasma display panel includes a substrate, a transparent electrode formed on the substrate, and an auxiliary electrode having a first part formed on the transparent electrode and a second part directly formed on the substrate, a dielectric layer formed on the transparent electrode and the first part of the auxiliary electrode, and an isolating layer formed between the substrate and the auxiliary electrode, at a position where the boundary of the dielectric layer intersects the upper surface of the auxiliary electrode. The isolating layer can prevent the auxiliary electrode from being peeled from the substrate.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: January 14, 2003
    Assignee: Acer Display Technology, Inc.
    Inventors: Yih-Jer Lin, Yao-Ching Su
  • Publication number: 20020132466
    Abstract: A method of forming a semiconductor device having reduced interconnect-line parasitic capacitance is provided. The method includes the following steps. First, a substrate is provided and a plurality of interconnect lines are formed on the substrate. A barrier layer is then formed. Next, the barrier layer is hardened and thinned so as to make the barrier layer having a thin-film attribute. Following that, a separation layer is formed by filling the space between and above the interconnect lines with a dielectric. Then, the dielectric is foamed. After that, an insulating layer is formed. Finally, the dielectric is condensed such that air gaps are formed in the separation layer.
    Type: Application
    Filed: August 29, 2001
    Publication date: September 19, 2002
    Inventors: Ben Min-Jer Lin, Sheng-Jen Wang
  • Publication number: 20020084750
    Abstract: An electrode structure of a plasma display panel (PDP) is disclosed. The electrode structure is formed on a front substrate of the PDP. The electrode structure includes a first sustaining electrode, a second sustaining electrode, and an auxiliary electrode. The first and second sustaining electrodes are formed on the substrate with a first gap existing there between. The auxiliary electrode is formed in the first gap. A second gap is formed between the auxiliary electrode and the second sustaining electrode. The second gap is smaller than the first gap.
    Type: Application
    Filed: May 10, 2001
    Publication date: July 4, 2002
    Inventors: Yao-Ching Su, Yih-Jer Lin
  • Patent number: 6344714
    Abstract: A plasma display panel device which can enlarge the bright region of a PDP with a given pixel size is provided. The auxiliary electrode of the plasma display panel device contacts not only the transparent electrode but also the substrate in order to avoid the auxiliary electrode being peeled off during the manufacturing process. Furthermore, the position of the auxiliary electrode is changed so the bright region between the pair of auxiliary electrodes is enlarged.
    Type: Grant
    Filed: November 29, 1999
    Date of Patent: February 5, 2002
    Assignee: Acer Display Technology, Inc.
    Inventors: Yao-Ching Su, Wen-Fa Sung, Yih-Jer Lin