Abstract: A data processing device for use with another data processing circuit sending data and requests for service thereto. The data processing device includes a processor circuit, a communication port connected to said processor circuit, having a data buffer including a plurality of registers comprising a first-in-first-out (FIFO) circuit and a plurality of external terminals, the communication port operative to communicate with the external terminals. Further included is a FIFO control unit, connected to the registers of the FIFO circuit, operative to provide FIFO control signals for data transfers between the communication port and the FIFO circuit. A port arbitration unit, connected to the FIFO control unit, has a port arbitration register and is operative to exchange port control signals for arbitrating port control between requests from the processor circuit and the external terminals. Other devices, systems and methods are also disclosed.

Abstract: A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address.

Abstract: An advanced video processor generates displays for displaying of either graphics or text information via a display monitor or a TV set operating as a monitor. The video processor includes a memory port, a graphics processor, at least one sprite register, a color palette, a color priority logic and a digital to analog converter. The color palette provides 512 color selections, any sixteen of which may be displayed at once.

Abstract: A data processing device comprising a storage circuit accessible by assertion of addresses, an arithmetic logic unit connected to the storage circuit operative to perform an arithmetic operation on data received by the arithmetic unit. Further included is an address register for storing an initial address word indicative of a storage circuit address. An instruction decode and control unit, connected to the storage circuit and having an instruction register operative to hold a program instruction is operative to decode the program instruction into control signals to control the operations of the data processing device and location codes to control data transfers according to predetermined sections of the program instruction wherein at least one of the sections includes a location section selecting the address register and a displacement section containing address data.

Abstract: An integrated circuit has a semiconductor die with a substrate and at least first and second bond pads. An internal circuit is fabricated on the semiconductor die and connected to the first bond pad. An electrostatic discharge protection circuit including cascaded bipolar transistors is connected in series with a field effect transistor between the first and second bond pads. In another version, an output buffer of the integrated circuit is divided into sections. An electrostatic discharge protection circuit is triggerable in response to a voltage in the substrate. Resistive connections are provided from the sections of the output buffer to one of the bond pads. The output buffer is operative upon an electrostatic discharge event to inject sufficient charge into the substrate to produce the voltage to trigger the electrostatic discharge protection circuit. Other circuits, devices, systems and methods are also disclosed.

Abstract: An integrated circuit has a clock input pad and circuitry operative in response to a clock signal. Clock transitions at the clock input pad are potentially subject to glitches due to noise and ringing. Further provided is a glitch remover circuit having a logic gate having first and second inputs. The glitch remover circuit has a series of circuits coupled to the clock input pad with differing delays for positive edges than for negative edges. The series of circuits has an output connected to the first input of the logic gate, with the second input coupled to the series of circuits intermediately. Other devices, systems and methods are also disclosed.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxilary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microcomputer has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxiliary arithmetic logic units, in parallel with one another, and which are each connected to a set address lines in a memory bus; the two auxiliary arithmetic logic units thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: An advanced video processor generates displays for displaying of either graphics or text information via a display monitor or a TV set operating as a monitor. A color palette is included in the advanced video processor for programming of the color of the display. The color palette provides 512 color selections, any sixteen of which may be displayed at once.

Abstract: A microcomputer is disclosed which is specifically designed for computation-intensive applications. The microcomputer contains on-chip RAM and ROM, and has peripheral ports for access of external memory and input/output functions. The microprocessor has a central processing unit with a floating-point multiplier in parallel with an arithmetic logic unit, and uses a plurality of registers as multiple accumulators. The central processing unit further contains two auxillary arithmetic logic units, in parallel with one another, and which are each connected to a set of address lines in a memory bus; the two auxillary arithmetic logic unit thus generate two separate memory addresses in parallel. The memory bus also contains one set of data lines, connected to the RAM and ROM, and to the central processing unit. The on-chip RAM and ROM are responsive to the two sets of address lines in time-multiplexed fashion to provide memory access via data lines twice per system clock cycle.

Abstract: An integrated on/off switch is provided that includes a latch that prevents the consumption of power by the switch during an "off" state. The switch circuits also includes the capability connected to the latch to activate a power supply during an "on" state and deactivate the power supply during the occurrence of an "off" state. Additionally the switch circuit includes the capability to reduce the direct current of the switch circuitry during "on" state. Lastly, the circuit includes the capability to alter the state of the latch upon the occurrence of a "off" signal or "on" signal. This switch can be monolithically integrated on a semiconductor substrate.

Abstract: A display circuit includes an input circuit to receive data to be displayed that is connected to segment output circuit which further includes a switching architecture that provides a switching signal of greater magnitude than the voltage supplied to the switch in order to provide output signals to a plurality of display segments. The display circuit further includes display timing circuit that provides a second switch which in turn provides a signal of greater magnitude than the magnitude of the voltage supply to the switch in order to provide output signals to the display segments to signify time intervals. The architecture of this display circuit is suitable for interface to liquid crystal display devices. The input interface is suitable for connection to a four bit microcomputer.

Abstract: A low power oscillator circuit including a latch connected to two loops. Each loop includes dynamic inverters and static inverters connected in cascade. The loops are connected to the latch such that the output of the final stage is an input to the latch. An initialization circuit is included on one loop to initiate oscillation. Storage capacitors are included in the loops to provide an oscillator output voltage that is greater than the oscillator power supply voltage.

Abstract: A digital clock generator circuit including a series of inverters connected in cascade with the output of the final stage connected to the input of the first stage in a ring counter fashion. Each inverter includes a first circuit to precharge a node, a second circuit to discharge a node upon occurrence of a selected input signal and a third circuit connected to isolate the node from the circuitry output during the precharge interval. The output of the counter is the output of the final stage. The inverter circuits allow for a low power digital counter by allowing a P-MOS or N-MOS fabrication of devices that do not require continuous power.

Abstract: A circuit that precharges a node and conditionally discharges the node according to the value of an input. This circuit also includes a device to isolate the node from the output line during precharge. This circuit can be fabricated as a positive channel metal oxide field effect transistor and can be structured to perform the logic function of an inverter or an NAND or NOR gate in simple form. This circuit also includes a capacitor that is connected to the precharge node such that additional charge provided by the clocking circuit is used to add charge to the node such that the charge at the node is greater than the charge provided by the circuit power supply alone.

Abstract: A memory cell includes a gated capacitor connected to a first node and also connected to a refresh line. The memory cell further includes a transistor that is also connected to the first node and to a second node with the gate terminal being connected to a second refresh line. The second node is connected to the bit line used to access the bit information contained in the cell. A second transistor is included that has one side connected to a power line, the second side connected to the second node and the gate terminal connected to the first node. A first refresh signal is provided on the refresh line connected to the gated capacitor and a second refresh signal is provided to the gate of the first transistor. The second refresh signal is of a voltage magnitude greater than the voltage provided on the power line and the second refresh signal is also provided at a time during which the first refresh signal is absent.

Abstract: A low current electronic oscillator system includes an oscillator tuning element, such as a piezoelectric crystal, operable at a predetermined frequency and an oscillator control circuit for cooperating with the tuning element to provide an oscillating electrical signal at the predetermined frequency. The control circuit includes first and second electrical charge storage devices coupled to a first portion of the tuning element; a first current drive device connectable to a first terminal of an applied electric potential and responsive to a first voltage on the first charge storage device for applying a first drive current to a second portion of the tuning element; and a second current drive device connectable to a second terminal of the electric potential and responsive to a second voltage on the second charge storage device for applying a second drive current to the second portion of the tuning element.

Abstract: A data processing system is disclosed having data processing means for providing data in either an encoded format or in a display format in respective first and second operating modes. Temperature compensated, liquid crystal display means responsive to the operating mode of the data processing means are provided for receiving the data provided thereby, converting any data received in the encoded format to the display format, and displaying all received data in the display format.

Abstract: Display information is stored in an array of segment latches, and by addressing these latches with common signals, the number of instructions necessary to operate a calculator in a display mode is greatly reduced. Thereby, the operation frequency of the calculator in the display only mode may be reduced, reducing the power consumption for CMOS devices.