Abstract: An ATV includes a removable passenger seat. The passenger seat is selectively added or removed from the ATV by way of a latch assembly. The passenger seat is supported by a pivot support link and a suspension coupling. The pivot support link and suspension coupling may be positioned rearward of a straddle-type seat for a driver. The entire pivot support link can be attached to the ATV in a dampened manner by way of the suspension coupling. The suspension coupling is comprised of at least one element acting in a linear direction and moving in at least a partially vertical travel component. The positioning of the suspension coupling provides greater vertical clearance, and therefore, maximum vertical stroke.

Abstract: An electrostatic discharge (ESD) protection circuit apparatus is disclosed. The apparatus includes activation circuitry coupled to a first node. The activation circuitry includes a capacitor and a selectable load. A time constant ? associated with the activation circuitry varies in accordance with the selectable load. The activation circuitry is configured to provide ?=?1 for detection of an ESD event. A shunt is selectively enabled by the activation circuitry to short the first node to a second node in accordance with the detection of the ESD event. The activation circuitry is configured subsequent detection of the ESD event to provide ?=?2, wherein ?2>?1.

Abstract: A feedback enhanced triggering device for an electrostatic discharge protection circuit includes: a first inverter 30b having an output coupled to an input of a second inverter 30c, the second inverter 30c having an output coupled to a control node for a discharge device 31 such as a transistor; a high side feedback transistor 34 coupled to the output of the first inverter 30b, and having a control node coupled to the output of the second inverter 30c; and a low side feedback transistor 35 coupled to the output of the first inverter 30b, and having a control node coupled to the output of the second inverter 30c, wherein the feedback transistors 34 and 35 provide enhanced triggering for electrostatic discharge protection.

Abstract: A feedback enhanced triggering device for an electrostatic discharge protection circuit includes: a first inverter 30b having an output coupled to an input of a second inverter 30c, the second inverter 30c having an output coupled to a control node for a discharge device 31 such as a transistor; a high side feedback transistor 34 coupled to the output of the first inverter 30b, and having a control node coupled to the output of the second inverter 30c; and a low side feedback transistor 35 coupled to the output of the first inverter 30b, and having a control node coupled to the output of the second inverter 30c, wherein the feedback transistors 34 and 35 provide enhanced triggering for electrostatic discharge protection.

Abstract: A semiconductor device (10) having a stacked-gate buffer (30) wherein the stacked-gate buffer (30) has a substrate (65) and a top substrate region (70) both with the same first conductivity type. The buffer (30) also has two transistors (95.105), each with a current carrying electrode and a control electrode (90, 100). A deep doped region (120) lies between the first (90) and second (100) control electrodes where the deep doped region (120) is another current carrying electrode for the first transistor (95) and another current carrying electrode for the second transistor (105) and the deep doped region (120) has a second conductivity that is opposite the first conductivity type. A deeper doped region (80) is also part of the stacked-gate buffer which has a second conductivity type and lies between the first (90) and second (100) control electrodes and is deeper than the deep doped region (120). A method of forming the device is also provided herein.

Abstract: A semiconductor device include a current source having a first node coupled to a first voltage reference node, and a second node for extracting a current in response to an electrostatic discharge (ESD) on a terminal. The device further includes a transistor having a well and a control electrode, a first current electrode coupled to a second voltage reference node, and a second current electrode coupled to the second node of the current source, and includes a resistive element is coupled to the terminal and the second node of the current source. The transistor of the semiconductor device is biased by detecting a positive voltage event (such as an ESD) at the first current electrode of the transistor, and biasing the first current electrode of the transistor in response to detecting the positive voltage event, wherein the biasing of the first current electrode is for preventing a forward biasing of an n-p junction associated with the transistor.

Abstract: A circuit (20) includes a resistor (26) and a current source (32) for raising the voltage of the source of the N-channel transistor in order to keep the base-emitter voltage of the parasitic bipolar device from forward biasing to prevent conduction in the parasitic bipolar device. In one embodiment, a relatively small resistor (26) is coupled between the source of an N-channel transistor (24) and ground. The current source (32) is used to direct some of the ESD current from a positive ESD event through the small source resistor (26) so that the source of the N-channel transistor (24) is elevated during the event, thus preventing snapback of the parasitic bipolar device.

Abstract: A semiconductor device including a current source having a first node coupled to a terminal, and a second node for extracting a current in response to an electrostatic discharge (ESD) on the terminal. The semiconductor device further including a transistor having a control electrode, a first current electrode coupled to the terminal, and a second current electrode coupled to the second node of the current source, and including a resistive element coupled to a first voltage reference node and the second node of the current source. The transistor of the semiconductor device is biased by detecting a negative voltage event (such as an ESD) at a first current electrode of the transistor and biasing a second current electrode of the transistor in response to detecting the negative voltage event, wherein the biasing of the second current electrode is for preventing a forward biasing of an p-n junction associated with the transistor.

Abstract: A semiconductor device (10) having a stacked-gate buffer (30) wherein the stacked-gate buffer (30) has a substrate (65) and a top substrate region (70) both with the same first conductivity type. The buffer (30) also has two transistors (95.105), each with a current carrying electrode and a control electrode (90, 100). A deep doped region (120) lies between the first (90) and second (100) control electrodes where the deep doped region (120) is another current carrying electrode for the first transistor (95) and another current carrying electrode for the second transistor (105) and the deep doped region (120) has a second conductivity that is opposite the first conductivity type. A deeper doped region (80) is also part of the stacked-gate buffer which has a second conductivity type and lies between the first (90) and second (100) control electrodes and is deeper than the deep doped region (120). A method of forming the device is also provided herein.

Abstract: A semiconductor device having a substrate with a first conductivity type. The substrate has a top substrate region that also has the first conductivity type. A first doped region, a second doped region and a third doped region are located in the top substrate region where the first and second doped regions have a second conductivity type opposite the first conductivity type while the third doped region has the first conductivity type and where the third doped region is between the first and second doped regions. A doped well region is also in the top substrate region and has the second conductivity type and has the second doped region and at least a portion of the third doped region located therein. A method of forming the device is also provided herein.

Abstract: A segmented bus architecture (800) removes certain ESD circuitry from each I/O pad cell (806, 812) and places it in a power pad cell (808, 814) or in some other unused area of the integrated circuit which incorporates the SBA. The removed ESD circuit is shared by several adjacent I/O pad cells via a segmented ESD bus. As a result, each individual I/O pad cell may be reduced in size.

Abstract: An electrostatic discharge (ESD) circuit (700) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a bipolar transistor (202). The bipolar device is triggered by a combination of an n-type MOSFET (702), a string of diodes (200), and a biasing circuit (704). The trigger point of the MOSFET is programmable by varying the number of individual diodes in the string of diodes. The relatively high transconductance of the n-type MOSFET allows the use of a smaller ESD circuit for a given degree of protection.

Abstract: An electrostatic discharge (ESD) circuit (12) provides robust protection to an input/output driver circuit (10). The discharge path is provided by a parasitic bipolar transistor (202). The parasitic bipolar device is triggered by a combination of a MOSFET (204) and a string of diodes (200). The trigger point of the MOSFET is programmable by varying the number of individual diodes in the string of diodes. A feedback circuit (602) ensures that MOSFET (204) is in a conductive state independent of the voltage state of the voltage supply, VDD, during an ESD event.

Abstract: A protection circuit (10) for a semiconductor-on-insulator device (20) allows an electrostatic event to occur at an input/output pad (12) without adversely affecting sensitive circuits, such as MOSFETs used in digital circuits. The protection circuit (10) allows the input/output pad (12) to be biased positively and negatively with respect to two different supply potentials and to other input/output pads on the chip. A body-tied MOSFET (14) is used in the protection circuit (10) where its drain regions (38) lie outside MOSFET's closed loop gate electrode (34).

Abstract: A thin film silicon on insulator circuit with a low voltage triggered, surface silicon controlled rectifier (30) for electrostatic damage protection and method is provided. A surface silicon controller rectifier (30) is formed in a thin device layer (130), overlying a buried insulation layer (110) and electrically coupled to a low voltage trigger apparatus (36). In one embodiment, a zener diode is employed as the low voltage trigger apparatus (36), and in another embodiment low voltage trigger apparatus (36) is an n-channel MOSFET.

Abstract: A body-tied MOSFET (14) is used in a protection circuit (10) of an SOI device (20) where the MOSFET's drain regions (38) lie outside MOSFET's closed-gate electrode (34). Electrical characteristics of the body-tied MOSFET (14) can be changed by varying the ratio of the total source region area to the total body-tied region area (tie frequency). The total electrical device width is the sum of the individual source region (36) widths. More charge can be placed on the drain region (38) compared to a drain region on the inside because the interfacial area between the drain region and channel region is larger. The device (20) can be formed without having to develop new processing steps or use marginal processing steps. Body ties to an underlying substrate are unnecessary.