Abstract: For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.

Abstract: A system and circuit for constructing a synchronous signal diagram from asynchronous sampled data provides a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.

Abstract: An integrated memory system with a spiral cache responds to requests for values at a first external interface coupled to a particular storage location in the cache in a time period determined by the proximity of the requested values to the particular storage location. The cache supports multiple outstanding in-flight requests directed to the same address using an issue table that tracks multiple outstanding requests and control logic that applies the multiple requests to the same address in the order received by the cache memory. The cache also includes a backing store request table that tracks push-back write operations issued from the cache memory when the cache memory is full and a new value is provided from the external interface, and the control logic to prevent multiple copies of the same value from being loaded into the cache or a copy being loaded before a pending push-back has been completed.

Abstract: Systolic networks within a tiled storage array provide for movement of requested values to a front-most tile, while making space for the requested values at the front-most tile by moving other values away. A first and second information pathway provide different linear pathways through the tiles. The movement of other values, requests for values and responses to requests is controlled according to a clocking logic that governs the movement on the first and second information pathways according to a systolic duty cycle. The first information pathway may be a move-to-front network of a spiral cache, crossing the spiral push-back network which forms the push-back network. The systolic duty cycle may be a three-phase duty cycle, or a two-phase duty cycle may be provided if the storage tiles support a push-back swap operation.

Abstract: A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.

Abstract: A system and circuit for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.

Abstract: A method, system and computer program product for generating device fingerprints and authenticating devices uses initial states of internal storage cells after each of a number multiple power cycles for each of a number of device temperatures to generate a device fingerprint. The device fingerprint may include pairs of expected values for each of the internal storage cells and a corresponding probability that the storage cell will assume the expected value. Storage cells that have expected values varying over the multiple temperatures may be excluded from the fingerprint. A device is authenticated by a similarity algorithm that uses a match of the expected values from a known fingerprint with power-up values from an unknown device, weighting the comparisons by the probability for each cell to compute a similarity measure.

Abstract: A method, test circuit and test system provide measurements to accurately characterize threshold voltage changes due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI). Both the bias temperature instability recovery profile and/or the bias temperature shifts due to rapid repetitions of stress application can be studied. In order to provide accurate measurements when stresses are applied at intervals on the order of tens of nanoseconds while avoiding unwanted recovery, and/or to achieve recovery profile sampling resolutions in the nanosecond range, multiple delay or ring oscillator frequency measurements are made using a delay line that is formed from delay elements that have delay variation substantially caused only by NBTI or PBTI effects. Devices in the delay elements are stressed, and then the delay line/ring oscillator is operated to measure a threshold voltage change for one or more measurement periods on the order of nanoseconds.

Abstract: A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.

Abstract: A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.

Abstract: Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.

Abstract: Data signals received in an integrated circuit are coupled to a receiver and to an on-chip data acquisition system which takes measurement samples of the data signal in response to a measurement request. The measurement request is synchronized with an asynchronous sample clock signal generating a capture signal and a counter reset signal. A counter measures the number of sample clock cycles between measurement requests. On receipt of a measurement request, the capture signal triggers the storage, as capture data, the preset number of cycles in the counter and the measurement samples in a register. The counter is synchronously reset and the capture data is sent to off-chip storage.

Abstract: For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature.

Abstract: For integrated circuits including circuit packaging and circuit communication technologies provision is made for a method of interconnecting or mapping a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array. Also provided is an arrangement for the interconnecting or mapping of a two-dimensional optoelectronic (OE) device array to a one-dimensional waveguide array.

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.