Patents by Inventor Jeremy D. Schaub

Jeremy D. Schaub has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080177489
    Abstract: A system and circuit for constructing a synchronous signal diagram from asynchronous sampled data provides a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.
    Type: Application
    Filed: March 26, 2008
    Publication date: July 24, 2008
    Inventors: Hayden C. Cranford, Fadi H. Gebara, Jeremy D. Schaub
  • Publication number: 20080159369
    Abstract: A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.
    Type: Application
    Filed: March 15, 2008
    Publication date: July 3, 2008
    Applicant: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Fadi H. Gebara, Jeremy D. Schaub
  • Publication number: 20080147340
    Abstract: Data signals received in an integrated circuit are coupled to a receiver and to an on-chip data acquisition system which takes measurement samples of the data signal in response to a measurement request. The measurement request is synchronized with an asynchronous sample clock signal generating a capture signal and a counter reset signal. A counter measures the number of sample clock cycles between measurement requests. On receipt of a measurement request, the capture signal triggers the storage, as capture data, the preset number of cycles in the counter and the measurement samples in a register. The counter is synchronously reset and the capture data is sent to off-chip storage. The off-chip storage stores an arbitrary amount of capture data and the area on-chip is greatly reduced for the on-chip data acquisition.
    Type: Application
    Filed: December 19, 2006
    Publication date: June 19, 2008
    Inventors: Fadi H. Gebara, Jeremy D. Schaub
  • Patent number: 7389192
    Abstract: A method for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 17, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Jr., Fadi H. Gebara, Jeremy D. Schaub
  • Patent number: 7383160
    Abstract: A method a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronously sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase to find a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 3, 2008
    Assignee: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Jr., Fadi H. Gebara, Jeremy D. Schaub
  • Publication number: 20080126010
    Abstract: A method a low cost and production-integrable technique for providing a signal diagram. The data signal is edge-detected and asynchronoulsy sampled (or alternatively a clock signal is latched). The data signal or a second signal is compared to a settable threshold voltage and sampled. The edge and comparison data are folded according to a swept timebase tofind a minimum jitter period. The crossing of the signal diagram edges is determined from a peak of a histogram of the folded edge data. A histogram of ratios of the sample values versus displacement from the position of the crossing location is generated for each threshold voltage. The technique is repeated over a range of settable threshold voltages. Then, the ratio counts are differentiated across the histograms with respect to threshold voltage, from which a signal diagram is populated.
    Type: Application
    Filed: June 30, 2006
    Publication date: May 29, 2008
    Inventors: Hayden C. Cranford, Fadi H. Gebara, Jeremy D. Schaub
  • Publication number: 20080113467
    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.
    Type: Application
    Filed: November 6, 2006
    Publication date: May 15, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jack O. Chu, Gabriel K. Dehlinger, Alfred Grill, Steven J. Koester, Qiqing Ouyang, Jeremy D. Schaub
  • Publication number: 20080042692
    Abstract: A comparator apparatus for comparing a first and a second voltage input includes a pair of cross-coupled inverter devices, including a pull up device and a pull down device, with output nodes defined between the pull up and pull down devices. A first switching device is coupled to the first input and a second switching device is coupled to the second input, with control circuitry configured for selective switching between a reset mode and a compare mode. In the reset mode, the first and second voltage inputs are coupled to respective output nodes so as to develop a differential signal thereacross, and the pull down devices in each inverter are isolated from the pull up devices. In the compare mode, the voltage inputs are isolated from the output nodes, and the pull down devices in each inverter are coupled to the pull up devices to latch the output nodes.
    Type: Application
    Filed: August 15, 2006
    Publication date: February 21, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fadi H. Gebara, Jeremy D. Schaub
  • Patent number: 7321269
    Abstract: An inverting circuit comprises a first inverter in a main path having a first input and a common ouput. A second inverter receives the first input and is coupled with a first voltage controlled pass gate to the common output. A third inverter couples a second input to the common output using a second voltage controlled pass gate. A fourth inverter couples the second input to the common output using the first voltage controlled pass gate. A ring oscillator is formed using a number N of the inverting circuits with each common output coupled to the first inputs forming a main ring of a ring oscillator. The second inputs are coupled to feed-forward signals from selected outputs. The resulting signals at the common outputs are an interpolation of the first and second input signals modulated by a control voltage coupled to the first and second pass gates.
    Type: Grant
    Filed: July 19, 2005
    Date of Patent: January 22, 2008
    Assignee: International Business Machines Corporation
    Inventors: Alan J. Drake, Fadi H. Gebara, Jeremy D. Schaub
  • Publication number: 20080004821
    Abstract: A method and apparatus for determining data signal jitter via asynchronous sampling provides a low cost and production-integrable mechanism for measuring data signal jitter. The data signal is edge-detected and sampled by a sampling clock of unrelated frequency the sampled values are collected in a histogram according to a folding of the samples around a timebase. The timebase is determined by sweeping to detect a minimum jitter for the folded data. The histogram for the correct estimated timebase period is representative of the probability density function of the location of data signal edges and the jitter characteristics are determined by the width and shape of the density function peaks. Frequency drift can be corrected by adjusting the timebase used to fold the data across the sample set.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Hayden C. Cranford, Jr., Fadi H. Gebara, Jeremy D. Schaub
  • Publication number: 20080002762
    Abstract: A sequence of K voltage samples of a transmitted data signal is generated by sampling, digitizing, and storing voltage samples of the data signal with an imbedded sample clock on an IC having an unknown period TS. The K voltage samples are plotted against a time base of K sequential times TB[K] normalized so all samples fall within one cycle of the data clock used to generate the data signal or a unit time of 1. The time base is generated by estimating the sample clock period TSE to be some multiple of 1/P where P is greater than K. Eye diagrams are analyzed for time jitter wherein only the minimum value of jitter is saved. TSE is incremented by 1/P until TS is greater than one half the data clock period. The eye diagram at the TSE with the minimum time jitter is used to analyze the data channels.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Hayden C. Cranford, Fadi H. Gebara, Jeremy D. Schaub
  • Patent number: 7286947
    Abstract: A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: October 23, 2007
    Assignee: International Business Machines Corporation
    Inventors: Hayden C. Cranford, Jr., Fadi H. Gebara, Jeremy D. Schaub
  • Patent number: 7138697
    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Gabriel K. Dehlinger, Alfred Grill, Steven J. Koester, Qiging Ouyang, Jeremy D. Schaub
  • Patent number: 6493077
    Abstract: An optical testing device includes an optical fiber having a first numerical aperture at a first end of the optical fiber. A positioning structure is attached to the optical fiber for moving the first end of the optical fiber to any portion of a substrate for testing an optical device. The optical device may be disposed at any location on the substrate and provides a light beam with an emission angle less than the first numerical aperture. A test head collects the light beam through the optical fiber to test the optical device. A method for positioning the optical fiber and testing the optical device is also disclosed.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: December 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: John D. Crow, Petar Pepeljugoski, Jeremy D. Schaub