Abstract: A device according to some embodiments includes a metal-insulator-metal (MIM) capacitor including a substrate, an upper metal plate, and a lower metal surface attached to a first surface of the substrate. The upper metal plate of the MIM capacitor is configured to serve as a wire bonding surface. Other embodiments include an RF transistor package and a device including a MIM capacitor that includes at least one via.

Abstract: In some aspects, a device includes a substrate. A first metallization arranged on the substrate. A second metallization arranged on the substrate. A circuit arranged on the substrate and electrically connected to the first metallization and the second metallization. The first metallization and the second metallization being configured, structured, and arranged to make a solder connection to a device, where the substrate may include silicon carbide (SiC).

Abstract: A transistor amplifier package includes a package substrate comprising conductive patterns exposed by solder mask patterns at a surface thereof, and at least one transistor die comprising a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask patterns such that respective gate, drain, and/or source terminals of the at least one transistor die are electrically connected to respective ones of the conductive patterns. Related transistor amplifiers and fabrication methods are also discussed.

Abstract: RF transistor amplifier circuits are provided that comprise a circuit board and an RF transistor amplifier die. The RF transistor amplifier die is flip-chip mounted on an upper surface of the circuit board so that a gate terminal, a drain terminal and a source terminal of the die face the upper surface of the circuit board. These RF transistor amplifier circuits further include a heatsink mounted on an upper surface of the RF transistor amplifier die and a plurality of surface mount circuit elements mounted on the upper surface of the circuit board so that a footprint of the heatsink vertically overlaps each of the plurality of surface mount circuit elements.

Abstract: A radio frequency (RF) transistor die includes a semiconductor structure having an active region including a plurality of transistors having respective gate, drain, or source fingers, and manifold on the semiconductor structure that electrically couples a plurality of the respective gate, drain, or source fingers. At least one capacitor is on the manifold and/or is on at least one of the respective gate, drain, or source fingers. The manifold may be a first metal layer on the semiconductor structure that provides a lower plate of the at least one capacitor, and a second metal layer on the semiconductor structure may provide an upper plate of the at least one capacitor. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device package includes a plurality of input leads and an output lead, a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads, and a combination circuit configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal to the output lead.

Abstract: An amplifier circuit that includes an RF amplifier; an impedance matching network; a higher order harmonic termination circuit; a fundamental frequency matching circuit; and an integrated passive device (IPD) that includes a silicon carbide (SiC) substrate. The integrated passive device (IPD) includes one or more reactive components of the fundamental frequency matching circuit and one or more reactive components of the higher order harmonic termination circuit.

Abstract: A monolithic microwave integrated circuit comprises a monolithic substrate, a Group III nitride-based channel layer on the monolithic substrate, a Group III nitride-based barrier layer on the monolithic substrate, a Group III nitride-based channel layer in between the monolithic substrate and the Group III nitride-based barrier layer, a radio frequency circuit that includes a plurality of depletion mode RF transistors that are formed in the Group III nitride-based channel and barrier layers, and a static random access memory (“SRAM”) circuit that includes a SRAM block having a plurality of SRAM cells arranged in rows and columns, the SRAM circuit including a plurality of depletion mode transistors and a plurality of enhancement mode transistors that are formed in the Group III nitride-based channel and barrier layers.

Abstract: A parallel and distributed query engine for federated searching is disclosed herein. As contemplated by the present disclosure, the system may provide a single application programming interface that allows a user to access and analyze multiple enterprise data storage locations remotely and simultaneously while presenting and reporting information from the multiple sources in a single, uniform display. Such a solution may allow a user to analyze and cross-reference data stored in multiple locations by using multiple queries in real time without requiring the actual data files to be displaced or combined. The system may further implement interactive artificial intelligence assistant, natural language processing, and workflow-based operations for improved user access and functionality.

Abstract: A gallium nitride-based RF transistor amplifier comprises a semiconductor layer structure comprising a barrier layer on a channel layer, first and second source/drain regions in the semiconductor layer structure, first and second source/drain contacts on the respective first and second source/drain regions, and a longitudinally-extending gate finger that is between the first and second source/drain contacts. The first and second source/drain contacts each has an inner sidewall that faces the gate finger and an opposed outer sidewall. The first source/drain region extends a first distance from a lower edge of the inner sidewall of the first source/drain contact towards the second source/drain region along a transverse axis that extends parallel to a plane defined by the upper surface of the semiconductor layer structure, and extends a second, smaller distance from a lower edge of the outer sidewall of the first source/drain contact away from the second source/drain region.

Abstract: Embodiments of the present invention provide methods, systems, and computer-readable storage medium for providing personalized navigation control items of an application. In an embodiment, a method includes receiving, from a user, at least one identification element of the user on a page of the application via a mobile computing device. The method includes transmitting, to a financial institution system, the user's identification element. Upon authenticating the user by the financial institution system, the method further includes receiving, at the mobile computing device, information related to personalization of navigation control items associated with a plurality of service sections of the application. The personalization of the navigation control items are generated by applying business rules to user data by the financial institution system. The navigation control items that personalized for the user's convenience and need are displayed on a page of the application on the mobile computing device.

Abstract: Semiconductor devices are provided that include a Group III nitride-based semiconductor layer structure. A first metal layer is formed on an upper surface of the semiconductor layer structure, a first dielectric layer is formed on an upper surface of the first metal layer, and a second metal layer is formed on an upper surface of the first dielectric layer. The first metal layer, the first dielectric layer and the second metal layer form a first capacitor. A second dielectric layer is formed on an upper surface of the second metal layer, a third dielectric layer is formed on an upper surface of the second dielectric layer, and a third metal layer is formed on upper surfaces of the second and third dielectric layers. The second metal layer, the second dielectric layer and the third metal layer form a second capacitor that is stacked on the first capacitor.

Abstract: A transistor device includes a semiconductor layer, source and drain contacts on the semiconductor layer, a gate contact on the semiconductor layer between the source and drain contacts, and a field plate over the semiconductor layer between the gate contact and the drain contact. The transistor device includes a first electrical connection between the field plate and the source contact that is outside an active region of the transistor device, and a second electrical connection between the field plate and the source contact.

Abstract: A transistor device includes a plurality of gate fingers that extend in a first direction and are spaced apart from each other in a second direction, each of the gate fingers comprising at least spaced-apart and generally collinear first and second gate finger segments that are electrically connected to each other. The first gate finger segments are separated from the second gate finger segments in the first direction by a gap region that extends in the second direction. A resistor is disposed in the gap region.

Abstract: An RF transistor package includes a metal submount; a transistor die mounted to the metal submount; and a surface mount IPD component mounted to the metal submount. The surface mount IPD component includes a dielectric substrate that includes a top surface and a bottom surface and at least a first pad and a second pad arranged on a top surface of the surface mount IPD component; at least one surface mount device includes a first terminal and a second terminal, the first terminal of the surface mount device mounted to the first pad and the second terminal mounted to the second pad; at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by the dielectric substrate; and at least one wire bond bonded to the at least one of the first pad and the second pad.

Abstract: A transistor device includes a metal submount; a transistor die arranged on said metal submount; a first integrated passive device (IPD) component that includes a first substrate arranged on said metal submount; and a second integrated passive device (IPD) component that includes a second substrate arranged on the metal submount. Additionally, the first substrate is a different material from the second substrate.

Abstract: A metal-insulator-metal (MIM) capacitor component that includes a substrate, where the metal-insulator-metal (MIM) capacitor component is configured to form a first capacitor with a top metal and a first bottom metal having a dielectric layer therebetween; and where the metal-insulator-metal (MIM) capacitor component is configured to form a second capacitor with the top metal and a second bottom metal having the dielectric layer therebetween. Additionally, the top metal, the dielectric layer, the first bottom metal, and the second bottom metal are arranged on the substrate.

Abstract: A transistor device includes a metal submount; a transistor die arranged on said metal submount; at least one integrated passive device (IPD) component that includes a substrate arranged on said metal submount; and one or more interconnects extending between the transistor die and the at least one integrated passive device (IPD) component. The substrate includes a silicon carbide (SiC) substrate.

Abstract: An RF transistor amplifier circuit comprises a Group III nitride based RF transistor amplifier having a gate terminal, a Group III nitride based self-bias circuit that includes a first Group III nitride based depletion mode high electron mobility transistor, the Group III nitride based self-bias circuit configured to generate a bias voltage, and a Group III nitride based depletion mode differential amplifier that is configured to generate an inverted bias voltage from the bias voltage and to apply the inverted bias voltage to the gate terminal of the Group III nitride based RF transistor amplifier. The Group III nitride based RF transistor amplifier, the Group III nitride based self-bias circuit and the Group III nitride based depletion mode differential amplifier are all implemented in a single die.