Patents by Inventor Jerimy Nelson
Jerimy Nelson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 7327583Abstract: A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power vias and ground vias may be routed from a first redistribution layer between the internal bond surface and the external bond surface to a second redistribution layer between the first redistribution layer and the external bond surface based on a via pattern. The via pattern may comprise routing a power via and a ground via adjacent one another spaced apart at a distance that is substantially equal to a minimum routing pitch associated with the multilayer substrate.Type: GrantFiled: September 13, 2004Date of Patent: February 5, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jerimy Nelson, Mark D. Frank, Peter Shaw Moldauer, Karl Bois
-
Patent number: 7326860Abstract: A multilayer substrate having a bonding surface is disclosed. One embodiment of the substrate may comprise a bypass capacitor connection pad disposed on the bonding surface. The bypass capacitor connection pad may have a bypass capacitor power pad and a bypass capacitor ground pad. The substrate may also comprise a plurality of power vias routed from the bypass capacitor power pad to a first redistribution layer spaced apart from the bonding surface and a plurality of ground vias routed from the bypass capacitor ground pad to the first redistribution layer. The substrate may further comprise a plurality of power and ground vias routed from the first redistribution layer to a second redistribution layer according to a power and ground via pattern array, wherein the plurality of ground vias are jogged at the first redistribution layer to the plurality of power vias to form the power and ground via pattern array.Type: GrantFiled: June 5, 2006Date of Patent: February 5, 2008Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jerimy Nelson, Mark D. Frank, Peter Shaw Moldauer, Gary Taylor, David Quint
-
Patent number: 7272806Abstract: A method and software product evaluate vias in an electronic design. One or more via sufficiency rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via sufficiency rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via sufficiency rules. The indicators are visual indicators (e.g., via insufficiency DRCs) on a graphical user interface, and/or a textual report summarizing violations.Type: GrantFiled: February 19, 2003Date of Patent: September 18, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Mark D. Frank, Jerimy Nelson, Nathan Bertrand
-
Patent number: 7143389Abstract: Systems and methods associated with generating node level bypass capacitor models are disclosed. One embodiment of a system may comprise a plurality of bypass capacitor circuit models associated with respective bypass capacitors and a node level model generator. The node level model generator may associate bypass capacitor information for a plurality of bypass capacitors from a data base associated with a multi-layer structure design with respective bypass capacitor circuit models to provide a node level capacitor model for the plurality of bypass capacitors.Type: GrantFiled: July 28, 2004Date of Patent: November 28, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Yong Wang, Mark D. Frank, Jerimy Nelson
-
System and method for integrating subcircuit models in an integrated power grid analysis environment
Patent number: 7143022Abstract: A system and method for integrating a plurality of subcircuit grids in a simulation environment. Upon obtaining a subcircuit layer of a particular granularity for each logical component of an electrical entity (e.g., a semiconductor die in a package and board environment), the nodes of a first subcircuit layer are interconnected to the nodes of a second subcircuit layer using a constraint-based search process.Type: GrantFiled: December 30, 2003Date of Patent: November 28, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Yong Wang, Mark Frank, Jerimy Nelson -
Patent number: 7137088Abstract: Systems and methods for determining a signal coupling coefficient for a line or trace in an electrical circuit layout are disclosed. The systems and methods include, for example, reading a threshold value for a signal coupling coefficient, identifying the line in a circuit design database, establishing a window around the line in which circuit elements will be included in a calculation of the signal coupling coefficient of the line, calculating a signal coupling coefficient of the line based upon the circuit elements in the window, flagging the line if the calculated coupling coefficient differs from the threshold value, flagging the target line with a design rule check if the threshold value exceeds the calculated coefficient and storing the design rule check in the circuit design database. Systems and methods for determining signal coupling coefficients for one or more vias or paths are also disclosed.Type: GrantFiled: May 4, 2004Date of Patent: November 14, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Mark D. Frank, Jerimy Nelson, Kari Bois
-
Publication number: 20060236276Abstract: A method is provided for evaluating trace signal coupling in an electronic design (e.g., a package design). In the method, one or more trace signal coupling rules are formulated. One or more trace pairs designed to carry differential signals are then processed to determine whether the inter-trace spacing between the trace pairs violates the trace signal coupling rules. An indicator (e.g., a DRC and/or a report) is generated to identify violated trace signal coupling rules. Processing of the electronic design may be scoped according one or a group of signal nets, or one or a group of levels of the package design.Type: ApplicationFiled: February 19, 2003Publication date: October 19, 2006Inventors: Mark Frank, Jerimy Nelson, Peter Modauer
-
Publication number: 20060225916Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.Type: ApplicationFiled: June 5, 2006Publication date: October 12, 2006Inventors: Jerimy Nelson, Mark Frank, Peter Moldauer, Gary Taylor, David Quint
-
Patent number: 7117464Abstract: A method is provided for evaluating trace signal coupling in an electronic design (e.g., a package design). In the method, one or more trace signal coupling rules are formulated. One or more trace pairs designed to carry differential signals are then processed to determine whether the inter-trace spacing between the trace pairs violates the trace signal coupling rules. An indicator (e.g., a DRC and/or a report) is generated to identify violated trace signal coupling rules. Processing of the electronic design may be scoped according one or a group of signal nets, or one or a group of levels of the package design.Type: GrantFiled: February 18, 2003Date of Patent: October 3, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Mark D. Frank, Jerimy Nelson, Peter Shaw Modauer
-
Patent number: 7078812Abstract: A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first differential signal line associated with a differential signal line pair at a first redistribution layer in a direction along the common plane, and jogging a second differential signal line associated with the differential signal line pair at a second redistribution layer along the common plane in a same direction as the first differential signal line to provide a substantially balanced differential signal line pair.Type: GrantFiled: August 30, 2004Date of Patent: July 18, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Mark D. Frank, Jerimy Nelson, Peter Shaw Moldauer
-
Patent number: 7075185Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.Type: GrantFiled: September 14, 2004Date of Patent: July 11, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jerimy Nelson, Mark D. Frank, Peter Shaw Moldauer, Gary Taylor, David Quint
-
Patent number: 7069095Abstract: According to at least one embodiment, a method comprises generating a data file having design parameters for an electrical design, and with a computer-executable program, accessing the data file and populating a computer-aided design (CAD) program's database with the design parameters.Type: GrantFiled: December 4, 2003Date of Patent: June 27, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Jerimy Nelson, Mark D. Frank, Karl Bois
-
Patent number: 7055124Abstract: A method is provided for evaluating signal deviations in an electronic design (e.g., a package design), including the steps of: formulating one or more signal deviation rules; processing the electronic design to determine whether the signal deviations violate the signal deviation rules; and generating an indicator (e.g., a DRC and/or report) associated with the electronic design to identify violated signal deviation rules. Processing of the electronic design may be scoped according one or a group of signal nets.Type: GrantFiled: February 19, 2003Date of Patent: May 30, 2006Assignee: Hewlett-Packard Development Company, L.P.Inventors: Mark D. Frank, Jerimy Nelson, David W. Quint
-
Publication number: 20060055049Abstract: A method for routing vias in a multilayer substrate from bypass capacitor pads is disclosed. One embodiment of a method may comprise arranging a bypass capacitor power pad spaced apart from a bypass capacitor ground pad on a first surface of the multilayer substrate, routing a plurality of power vias from the bypass capacitor power pad to a first redistribution layer spaced from the first surface, and routing a plurality of ground vias from the bypass capacitor ground pad to the first redistribution layer. The methodology may further comprise jogging the plurality of ground vias at the first redistribution layer to the plurality of power vias to provide a power and ground via pattern, and routing the power and ground vias from the first redistribution layer to a second redistribution layer spaced apart from the first redistribution layer based on the power and ground via pattern.Type: ApplicationFiled: September 14, 2004Publication date: March 16, 2006Inventors: Jerimy Nelson, Mark Frank, Peter Moldauer, Gary Taylor, David Quint
-
Publication number: 20060055022Abstract: A method for routing vias in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with an internal bond surface having a plurality of internal bond pads and an external bond surface with a plurality of external bond pads. A plurality of power vias and ground vias may be routed from a first redistribution layer between the internal bond surface and the external bond surface to a second redistribution layer between the first redistribution layer and the external bond surface based on a via pattern. The via pattern may comprise routing a power via and a ground via adjacent one another spaced apart at a distance that is substantially equal to a minimum routing pitch associated with the multilayer substrate.Type: ApplicationFiled: September 13, 2004Publication date: March 16, 2006Inventors: Jerimy Nelson, Mark Frank, Peter Moldauer, Karl Bois
-
Publication number: 20060043537Abstract: A method for routing signals in a multilayer substrate is disclosed. One embodiment of a method may comprise providing a multilayer substrate with at least one differential signal line pair aligned along a common plane that is substantially transverse to a top surface of the multilayer substrate, jogging a first differential signal line associated with a differential signal line pair at a first redistribution layer in a direction along the common plane, and jogging a second differential signal line associated with the differential signal line pair at a second redistribution layer along the common plane in a same direction as the first differential signal line to provide a substantially balanced differential signal line pair.Type: ApplicationFiled: August 30, 2004Publication date: March 2, 2006Inventors: Mark Frank, Jerimy Nelson, Peter Moldauer
-
Publication number: 20060026542Abstract: Systems and methods associated with generating node level bypass capacitor models are disclosed. One embodiment of a system may comprise a plurality of bypass capacitor circuit models associated with respective bypass capacitors and a node level model generator. The node level model generator may associate bypass capacitor information for a plurality of bypass capacitors from a data base associated with a multi-layer structure design with respective bypass capacitor circuit models to provide a node level capacitor model for the plurality of bypass capacitors.Type: ApplicationFiled: July 28, 2004Publication date: February 2, 2006Inventors: Yong Wang, Mark Frank, Jerimy Nelson
-
Publication number: 20050251769Abstract: Various embodiments of a system, apparatus and method for determining the signal coupling coefficient of a path in the design of a substrate are disclosed. One apparatus embodiment comprises a path signal coupling coefficient tool.Type: ApplicationFiled: May 4, 2004Publication date: November 10, 2005Inventors: Mark Frank, Jerimy Nelson, Karl Bois
-
Publication number: 20050251770Abstract: Various embodiments of a system, apparatus and method for determining the signal coupling coefficient of a line in the design of a substrate are disclosed. One apparatus embodiment comprises a line signal coupling coefficient tool.Type: ApplicationFiled: May 4, 2004Publication date: November 10, 2005Inventors: Mark Frank, Jerimy Nelson, Kari Bois
-
Publication number: 20050249479Abstract: Various embodiments of a system, apparatus and method for determining the signal coupling coefficient of a via in the design of a substrate are disclosed. One apparatus embodiment comprises a via signal coupling coefficient tool.Type: ApplicationFiled: May 4, 2004Publication date: November 10, 2005Inventors: Mark Frank, Jerimy Nelson, Karl Bois