Abstract: A method for verifying coupling in a differential via pair group includes identifying a differential via pair group in a design database and identifying a victim differential via pair in the differential via pair group. All other differential via pairs in the differential via pair group are identified as culprit differential pairs. The differential via pair group includes at least one culprit differential via pair. The method also includes obtaining a total coupling threshold level and calculating a total coupling factor for the victim differential via pair within the differential via pair group. The method also includes flagging the victim differential via pair if the calculated total coupling factor exceeds the total coupling threshold level.

Abstract: A method for verifying coupling in a differential trace pair group includes reading victim properties of a victim differential trace pair and culprit properties of a plurality of culprit differential trace pairs from a circuit design database. The method also includes calculating a plurality of coupling factors based on the victim properties and the culprit properties, one from each of the plurality of culprit differential trace pairs to the victim differential trace pair. The method also includes calculating a total coupling factor for the victim differential trace pair based on the plurality of coupling factors, and flagging the victim differential trace pair if the total coupling factor exceeds a total coupling threshold level.

Abstract: A method for calculating worst case coupling for a differential pair group includes identifying a victim differential pair and at least one culprit differential pair in the differential pair group, calculating a coupling factor between each of the culprit differential pairs and the victim differential pair, and summing the absolute value of each of the coupling factors to generate a worst case coupling factor.

Abstract: A method evaluates signal trace discontinuities in an electronic design of the type having one or more traces. The method includes the steps of formulating one or more trace discontinuity rules, processing the electronic design to determine whether the traces violate the trace discontinuity rules, and generating an indicator (e.g., a DRC) associated with the electronic design to identify violated trace discontinuity rules. Each level, each signal net, or a group of signal nets may be evaluated, for example, to ensure compliance with the trace discontinuity rules.

Abstract: According to at least one embodiment, a system comprises logic for maintaining homogeneity between a model of an object designed in a computer-aided modeling system and corresponding parameter information for the model included in a model documentation file.

Abstract: A method evaluates signal trace discontinuities in an electronic design of the type having one or more traces. The method includes the steps of formulating one or more trace discontinuity rules, processing the electronic design to determine whether the traces violate the trace discontinuity rules, and generating an indicator (e.g., a DRC) associated with the electronic design to identify violated trace discontinuity rules. Each level, each signal net, or a group of signal nets may be evaluated, for example, to ensure compliance with the trace discontinuity rules.

Abstract: Techniques are disclosed for verifying the proximity of ground vias to signal vias in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a ground via within a predetermined threshold distance of each specified signal via in the package design. The proximity verifier may notify the package designer of any signal vias which are not sufficiently close to ground vias, such as by providing visual indications of such signal vias in a graphical representation of the package design displayed on a display monitor. In response, the package designer may modify the package model to ensure that all signal vias are sufficiently close to ground vias. The proximity verifier may be implemented as a design rule which may be executed automatically and in real-time by the package design tool.

Abstract: A method and software product evaluate vias, per pad, in an electronic design. One or more via per pad rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via per pad rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via per pad rules. The indicators are visual indicators (e.g., via per pad DRCs) on a graphical user interface, and/or a textual report summarizing violations.

Abstract: According to at least one embodiment, a method comprises generating a data file having design parameters for an electrical design, and with a computer-executable program, accessing the data file and populating a computer-aided design (CAD) program's database with the design parameters.

Abstract: In one aspect, techniques are disclosed for identifying and notifying a circuit designer of signal traces in an integrated circuit design that are closer to each other than a proximity threshold. It is desirable that signal traces be separated from each other by at least the proximity threshold to reduce inter-signal crosstalk to an acceptable level. Such notification may occur either dynamically (while the circuit designer is designing the circuit) or through a report generated after the circuit design has been generated. In another aspect, techniques are disclosed for identifying and notifying the circuit designer of the signal traces that are closest to a reference signal trace. Such notification may provide the circuit designer with feedback about regions in the circuit design which are congested and which may therefore produce an unacceptable level of crosstalk.

Abstract: A method is provided for evaluating via signal coupling in an electronic design (e.g., a package design). In the method, one or more via signal coupling rules are formulated. One or more via pairs designed to carry differential signals are then processed to determine whether the inter-via spacing between the via pairs violates the via signal coupling rules. An indicator (e.g., a DRC and/or a report) is generated to identify violated via signal coupling rules. Processing of the electronic design may be scoped according one or a group of signal nets, or one or a group of levels of the package design.

Abstract: A method is provided for evaluating signal deviations in an electronic design (e.g., a package design), including the steps of: formulating one or more signal deviation rules; processing the electronic design to determine whether the signal deviations violate the signal deviation rules; and generating an indicator (e.g., a DRC and/or report) associated with the electronic design to identify violated signal deviation rules. Processing of the electronic design may be scoped according one or a group of signal nets.

Abstract: A method and software product evaluate vias in an electronic design. One or more via sufficiency rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via sufficiency rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via sufficiency rules. The indicators are visual indicators (e.g., via insufficiency DRCs) on a graphical user interface, and/or a textual report summarizing violations.

Abstract: A method is provided for evaluating trace signal coupling in an electronic design (e.g., a package design). In the method, one or more trace signal coupling rules are formulated. One or more trace pairs designed to carry differential signals are then processed to determine whether the inter-trace spacing between the trace pairs violates the trace signal coupling rules. An indicator (e.g., a DRC and/or a report) is generated to identify violated trace signal coupling rules. Processing of the electronic design may be scoped according one or a group of signal nets, or one or a group of levels of the package design.

Abstract: A method and software product evaluate vias, per pad, in an electronic design. One or more via per pad rules are formulated, and then the electronic design is processed to determine whether the vias of the electronic design violate the via per pad rules. In the event of a violation, one or more indicators are generated to identify vias that violate the via per pad rules. The indicators are visual indicators (e.g., via per pad DRCs) on a graphical user interface, and/or a textual report summarizing violations.

Abstract: A method evaluates signal trace discontinuities in an electronic design of the type having one or more traces. The method includes the steps of formulating one or more trace discontinuity rules, processing the electronic design to determine whether the traces violate the trace discontinuity rules, and generating an indicator (e.g., a DRC) associated with the electronic design to identify violated trace discontinuity rules. Each level, each signal net, or a group of signal nets may be evaluated, for example, to ensure compliance with the trace discontinuity rules.

Abstract: Techniques are disclosed for verifying the proximity of signal return paths (e.g., ground metal or power) to signal traces in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a signal return path within a predetermined threshold distance of each specified signal trace in the package layers directly above and/or below the signal trace. The proximity verifier may notify the package designer of any signal traces which are not sufficiently close to signal return paths, such as by providing visual indications of such signal traces in a graphical representation of the package design. In response, the package designer may modify the package model to ensure that all signal traces are sufficiently close to signal return paths.

Abstract: In one aspect, techniques are disclosed for identifying and notifying a circuit designer of signal traces in an integrated circuit design that are closer to each other than a proximity threshold. It is desirable that signal traces be separated from each other by at least the proximity threshold to reduce inter-signal crosstalk to an acceptable level. Such notification may occur either dynamically (while the circuit designer is designing the circuit) or through a report generated after the circuit design has been generated. In another aspect, techniques are disclosed for identifying and notifying the circuit designer of the signal traces that are closest to a reference signal trace. Such notification may provide the circuit designer with feedback about regions in the circuit design which are congested and which may therefore produce an unacceptable level of crosstalk.

Abstract: Techniques are disclosed for verifying the proximity of signal return paths (e.g., ground metal or power) to signal traces in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a signal return path within a predetermined threshold distance of each specified signal trace in the package layers directly above and/or below the signal trace. The proximity verifier may notify the package designer of any signal traces which are not sufficiently close to signal return paths, such as by providing visual indications of such signal traces in a graphical representation of the package design. In response, the package designer may modify the package model to ensure that all signal traces are sufficiently close to signal return paths.

Abstract: Techniques are disclosed for verifying the proximity of ground vias to signal vias in an integrated circuit package design. A package designer creates the package design using a package design tool. A proximity verifier verifies that there is a ground via within a predetermined threshold distance of each specified signal via in the package design. The proximity verifier may notify the package designer of any signal vias which are not sufficiently close to ground vias, such as by providing visual indications of such signal vias in a graphical representation of the package design displayed on a display monitor. In response, the package designer may modify the package model to ensure that all signal vias are sufficiently close to ground vias. The proximity verifier may be implemented as a design rule which may be executed automatically and in real-time by the package design tool.