Abstract: A semiconductor device having low-leakage borderless contacts is formed by etching contact openings adjacent first and second electronic elements of opposite dopant type, conformally depositing a thin doped polysilicon layer, protecting the electronic element of similar dopant-type, removing the thin doped polysilicon layer adjacent the oppositely doped electronic element, diffusing dopant from said polysilicon layer into a side wall of the electronic element of similar dopant-type, and then depositing tungsten within the contact openings.

Abstract: The invention provides a method for electrically connecting a trench capacitor and a diffusion region, and also for electrically connecting a trench capacitor or a diffusion region with external circuitry in a semiconductor device. The method provides for formation of a strap or bridge contact by formation of strap holes exposing the electrical elements utilizing an oxide insulation layer and a nitride etch stop and a highly selective oxide:nitride etch and a selective nitride:oxide etch. The strap holes may then be filled with an electrical conductor.

Abstract: A silicon nitride layer in a semiconductor device is oxidized by exposure to a mixture of an oxygen reactant and a dilute amount of a fluorine-containing compound at a temperature sufficiently high to substantially cause the oxidation of the silicon nitride. Generally, a temperature greater than about 600.degree. C. is sufficient to cause such oxidation, although some oxidation may occur at lower temperatures. The concentration of the fluorine-containing compound is also not critical, but is generally between about 100 to 1500 ppm by volume relative to the total mixture volume. Preferably, NF.sub.3 is the fluorine-containing compound, and a temperature greater than about 700.degree. C. at a concentration of between about 100 to 1000 ppm is used.

Abstract: A memory cell, suitable for electrically erasable programmable read only memories (EEPROMs), includes direct write cell capability. The memory cell is fabricated on a substrate and uses an inversion source gate disposed above the substrate to generate a depletion source therein. The depletion source defines a channel region in the substrate with an associated drain. An electrically isolated floating gate is disposed above the substrate so as to overlap at least a portion of the substrate channel region. Further, a program gate is disposed to overlap a portion of the floating gate and an access gate is also provided aligned at least partially over the substrate channel region such that a dual gate device is defined. An array of such memory cells can also be constructed.

Abstract: An improved contactless temperature measurement system is provided which includes a workpiece, a chamber containing the workpiece with the walls thereof being substantially transmissive to radiation at wavelengths other than a given wavelength and substantially reflective at the given wavelength to remove the dependence of the apparent or measured temperature on the workpiece emissivity variations or fluctuations.

Abstract: The invention provides a method for electrically connecting a polysilicon-filled trench to a diffusion region in a semiconductor device, wherein the trench and diffusion region are separated by a dielectric. The method provides for formation of a strap or bridge contact by utilizing a diffusion barrier layer which prevents diffusion into an overlying polysilicon layer when a subsequent boron out-diffusion step is performed. Selective etching is then utilized to remove the polysilicon layer where no boron has diffused, leaving a polysilicon strap connecting the trench and diffusion region.

Abstract: A method for self-aligning an isolation structure to a diffusion region. A first masking layer is formed on a semiconductor substrate, the first masking layer having at least one aperture sidewall which is substantially perpendicular to the semiconductor substrate. Dopant ions are implanted into the semiconductor substrate through the first masking layer to form a doped region. Sidewall spacers are then defined on the sidewalls of the aperture, and a sidewall image reversal process is carried out such that the sidewall spacers define trench apertures in a masking structure. Finally, isolation trenches are etched into the semiconductor substrate through the masking structure. Alternatively, the implantation step is carried out after the sidewall spacers are defined on the first masking layer.

Abstract: A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes are then formed on the substrate, to provide low sheet resistance source and drain electrodes. An insulating layer is then formed on the substrate, and is planarized to expose an upper surface of the gate mask. The gate mask is then removed in wet H.sub.3 PO.sub.4 to define an aperture in the insulating layer that exposes the polysilicon layer, and a conductive material is selectively grown on the substrate to provide a metal-strapped polysilicon gate electrode that is relatively co-planar with the planarized insulating layer.

Abstract: A method of improving silicon-on-insulator uniformity using polishing. A polishing stop layer of substantially uniform thickness is provided having a first side which is made coplanar with a first side of a thicker layer of semiconductor material. A polishing process is applied to a second side of the semiconductor material until a second side of the polishing stop layer is encountered, such that the substantially uniform thickness of the polishing stop layer can be used to define the semiconductor material to a layer of uniform thickness.

Abstract: A method of fabricating a shared element semiconductor structure in which the insulating layer of a silicon-on-insulator structure is patterned to form a gate oxide. The bulk semiconductor underlying the insulating layer is defined into an FET (field-effect transistor) with its gate region below the gate oxide. The epitaxial layer above the insulating layer is defined into another FET with its drain region above the gate oxide, whereby the drain region also operates as the gate electrode for the bulk FET. Also described is a method of forming a silicon on insulator substrate with insulating layer usable as a gate oxide by means of bonding a silicon substrate to an oxidized epitaxial layer on another silicon seed substrate and then removing the seed substrate.

Abstract: A method of forming a thin silicon layer upon which semiconductor devices may be constructed. An epitaxial layer is grown on a silicon substrate, and oxygen or nitrogen ions are implanted into the epitaxial layer in order to form a buried etch-stop layer therein. An oxide layer is grown on the epitaxial layer, and is used to form a bond to a mechanical support wafer. The silicon substrate is removed using grinding and/or HNA, the upper portions of the epitaxy are removed using EDP, EPP or KOH, and the etch-stop is removed using a non-selective etch. The remaining portions of the epitaxy forms the thin silicon layer. Due to the uniformity of the implanted ions, the thin silicon layer has a very uniform thickness.

Abstract: A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers.

Abstract: A method is provided for manufacturing semiconductor structures having dielectrically isolated silicon regions on one side of a silicon body. This is accomplished by forming in the silicon body a set of buried regions and a set of surface regions having characteristics which make them anodically etch slower than the remaining portion of the silicon body. These two sets of regions define portions in the silicon body which are anodically etched to form porous silicon regions which are oxidized to form an isolation structure that isolates the silicon surface regions from each other and the remaining portion of the silicon body. Typically in a P-type silicon body the buried and surface regions are N-type regions formed through ion implantation.

Abstract: A method for annealing ion implanted regions buried in a semiconductor substrate without the undesirable effects of thermal diffusion which includes the radiation of the substrate by a continuous laser having an emission frequency longer than 600 nanometers which the buried ion implanted regions will absorb strongly but which will be substantially unabsorbed by the unimplanted regions.Superior results can be obtained when the substrate is heated to approximately 300.degree. during this laser annealing.

Abstract: A thermoluminescent phosphor comprising LiF doped with boron and magnesium is produced by diffusion of boron into a conventional LiF phosphor doped with magnesium. Where the boron dopant is made to penetrate only the outer layer of the phosphor, it can be used to detect shallowly penetrating radiation such as tritium beta ays in the presence of a background of more penetrating radiation.

Abstract: A thermoluminescent phosphor comprising LiF doped with boron and magnesium is produced by diffusion of boron into a conventional LiF phosphor doped with magnesium. Where the boron dopant is made to penetrate only the outer layer of the phosphor, it can be used to detect shallowly penetrating radiation such as tritium beta rays in the presence of a background of more penetrating radiation.