Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Abstract: Structures and methods for Flash memory with low tunnel barrier intergate insulators are provided. The non-volatile memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate. A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate. A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: Structures and methods for programmable array type logic and/or memory with p-channel devices and asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include p-channel non-volatile memory which has a first source/drain region and a second source/drain region separated by a p-type channel region in an n-type substrate. A floating gate opposing the p-type channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

Abstract: Structures and methods for programmable array type logic and/or memory devices with asymmetrical low tunnel barrier intergate insulators are provided. The programmable array type logic and/or memory devices include non-volatile memory which has a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by an asymmetrical low tunnel barrier intergate insulator formed by atomic layer deposition. The asymmetrical low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3.

Abstract: A semiconductor die having multiple solder bumps, each having a diameter less than about 100 microns, and the method for making such a die are described. The solder bumps are preferably about 10 microns in diameter, and the pitch between the solder bumps is less than 100 microns, and preferably less than or equal to 10 microns. A thermal solder jet apparatus is utilized to deposit solder material to form the solder bumps. The apparatus includes a print head having a plurality of solder ejection ports. Each ejection port has an associated gas ejection conduit connected to a chamber containing one or more hydride films. The hydride film is heated to disassociate hydrogen gas. The hydrogen gas rapidly builds up in the conduit which leads to the ejection port which is loaded with a solder material and forces the ejection of the solder material from the port.

Abstract: An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel with a first region and a second region. An actuator is disposed in the actuator channel and is movable when in a flowable state between a first position and a second position. A heater is positioned proximate to the actuator channel to heat the actuator from a solid state to a flowable state. A source of gas or other propellant is positioned proximate to the actuator channel to drive the actuator from the first position to the second position. The actuator has a higher surface tension when engaged with the second region of the channel than when engaged with the first region. Accordingly, the actuator can halt upon reaching the second region of the channel due to the increased surface tension between the actuator and the second region of the channel.

Abstract: A multi-chip electronic package comprised of a plurality of integrated circuit chips secured together in a stack formation. The chip stack is hermetically sealed in an enclosure. The enclosure comprises a pressurized, thermally conductive fluid, which is utilized for cooling the enclosed chip stack. A process and structure is proposed that allows for densely-packed, multi-chip electronic packages to be manufactured with improved heat dissipation efficiency, thus improving the performance and reliability of the multi-chip electronic package.

Abstract: An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel with a first region and a second region. An actuator is disposed in the actuator channel and is movable when in a flowable state between a first position and a second position. A heater is positioned proximate to the actuator channel to heat the actuator from a solid state to a flowable state. A source of gas or other propellant is positioned proximate to the actuator channel to drive the actuator from the first position to the second position. The actuator has a higher surface tension when engaged with the second region of the channel than when engaged with the first region. Accordingly, the actuator can halt upon reaching the second region of the channel due to the increased surface tension between the actuator and the second region of the channel.

Abstract: An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel with a first region and a second region. An actuator is disposed in the actuator channel and is movable when in a flowable state between a first position and a second position. A heater is positioned proximate to the actuator channel to heat the actuator from a solid state to a flowable state. A source of gas or other propellant is positioned proximate to the actuator channel to drive the actuator from the first position to the second position. The actuator has a higher surface tension when engaged with the second region of the channel than when engaged with the first region. Accordingly, the actuator can halt upon reaching the second region of the channel due to the increased surface tension between the actuator and the second region of the channel.

Abstract: A semiconductor die having multiple solder bumps, each having a diameter less than about 100 microns, and the method for making such a die are described. The pitch between the solder bumps is less than 100 microns. A thermal solder jet apparatus is utilized to deposit solder material to form the solder bumps. The apparatus includes a print head having a plurality of solder ejection ports. Each ejection port has an associated gas ejection conduit connected to a chamber containing one or more hydride films for producing hydrogen gas. The hydrogen gas is utilized to force the ejection of the solder material from the ejection port. A controller controls and choreographs the movements of the movable substrate and movable drive so as to accurately deposit material in desired locations on the semiconductor dies.

Abstract: A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using devices and methods described above. Further, devices and methods provided are able to operate at temperatures much higher than other print head designs such as piezoelectric actuated print heads. Additionally, due to the use of a gas flow restricting device and a recharging gas supply, ejection devices as described above can be used for a substantially extended lifetime, thus making devices and methods described above more economically desirable.

Abstract: A method and device for printing liquid material such as liquid solder is provided. C4 structures as small as 10 microns in diameter can be produced using devices and methods described above. Further, devices and methods provided are able to operate at temperatures much higher than other print head designs such as piezoelectric actuated print heads. Additionally, due to the use of a gas flow restricting device and a recharging gas supply, ejection devices as described above can be used for a substantially extended lifetime, thus making devices and methods described above more economically desirable.

Abstract: A method and device for reducing a dopant diffusion rate in a doped semiconductor region is provided. The methods and devices include selecting a plurality of impurity elements, including at least one dopant element. Selection of a plurality of impurity elements includes selecting a first impurity element with a first atomic radius larger than an average host matrix atomic radius and selecting a second impurity element with a second atomic radius smaller than an average host matrix atomic radius. The methods and devices further include selecting amounts of each impurity element of the plurality of impurity elements wherein amounts and atomic radii of each of the plurality of impurity elements complement each other to reduce a host matrix lattice strain.

Abstract: Structures and methods for DEAPROM memory with low tunnel barrier intergate insulators are provided. The DEAPROM memory includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator having a tunnel barrier of less than 1.5 eV. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of NiO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5, Y2O3, Gd2O3, SrBi2Ta2O3, SrTiO3, PbTiO3, and PbZrO3. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.