Patents by Inventor Jerome Teysseyre
Jerome Teysseyre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230071048Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Applicant: STMICROELECTRONICS PTE LTDInventors: Jing-En LUAN, Jerome TEYSSEYRE
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Publication number: 20230075519Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.Type: ApplicationFiled: November 14, 2022Publication date: March 9, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Maria Cristina ESTACIO, Seungwon IM
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Publication number: 20230019930Abstract: Implementations of a semiconductor package may include one or more power semiconductor die included in a die module; a first heat sink directly coupled to one or more source pads of the die module; a second heat sink directly coupled to one or more drain pads of the die module; a gate contact coupled with one or more gate pads of the die module; and a coating coupled directly to the die module. The gate contact may be configured to extend through an immersion cooling enclosure.Type: ApplicationFiled: June 15, 2022Publication date: January 19, 2023Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Inpil YOO, Jerome TEYSSEYRE, Oseob JEON, Keunhyuk LEE, Michael J. SEDDON
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Patent number: 11545421Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.Type: GrantFiled: January 28, 2021Date of Patent: January 3, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Maria Cristina Estacio, Seungwon Im
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Publication number: 20220406767Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.Type: ApplicationFiled: August 29, 2022Publication date: December 22, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Inpil YOO, JooYang EOM
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Publication number: 20220406744Abstract: Implementations of semiconductor devices may include a die coupled over a lead frame, a redistribution layer (RDL) coupled over the die, a first plurality of vias coupled between the RDL and the die, and a second plurality of vias coupled over and directly to the lead frame. The second plurality of vias may be adjacent to an outer edge of the semiconductor device and may be electrically isolated from the die.Type: ApplicationFiled: May 24, 2022Publication date: December 22, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jooyang EOM, Seungwon IM, Maria Cristina ESTACIO, Jerome TEYSSEYRE, Inpil YOO
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Publication number: 20220406684Abstract: Implementations of a semiconductor package may include one or more semiconductor die directly coupled to only a direct leadframe attach (DLA) leadframe including two or more leads; and a coating covering the one or more semiconductor die and the DLA leadframe where when the semiconductor package is coupled into an immersion cooling enclosure, the coating may be in contact with a dielectric coolant while the two or more leads extend out of the immersion cooling enclosure.Type: ApplicationFiled: May 23, 2022Publication date: December 22, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Oseob JEON, Youngsun KO, Seungwon IM, Jerome TEYSSEYRE, Michael J. SEDDON
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Patent number: 11513220Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.Type: GrantFiled: September 5, 2019Date of Patent: November 29, 2022Assignee: STMICROELECTRONICS PTE LTDInventors: Jing-En Luan, Jerome Teysseyre
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Patent number: 11502027Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.Type: GrantFiled: January 28, 2021Date of Patent: November 15, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Maria Cristina Estacio, Seungwon Im
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Patent number: 11430777Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.Type: GrantFiled: November 19, 2020Date of Patent: August 30, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome Teysseyre, Inpil Yoo, JooYang Eom
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Publication number: 20220238421Abstract: A semiconductor device package may include a leadframe having a first portion with first extended portions and a second portion with second extended portions. Mold material may encapsulate a portion of the leadframe and a portion of a semiconductor die mounted to the leadframe. A first set of contacts of the semiconductor die may be connected to a first surface of the first extended portions, while a second set of contacts may be connected to a first surface of the second extended portions. A mold-locking cavity having the mold material included therein may be disposed in contact with a second surface of the first extended portions opposed to the first surface of the first extended portions, a second surface of the second extended portions opposed to the first surface of the second extended portions, the first portion of the leadframe, and the second portion of the leadframe.Type: ApplicationFiled: January 22, 2021Publication date: July 28, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Maria Clemens Ypil QUINONES, Bigildis DOSDOS, Jerome TEYSSEYRE, Erwin Ian Vamenta ALMAGRO, Romel N. MANATAD
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Publication number: 20220173022Abstract: Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.Type: ApplicationFiled: February 18, 2022Publication date: June 2, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Inpil YOO, Seungwon IM, JooYang EOM, Jerome TEYSSEYRE
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Publication number: 20220157801Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.Type: ApplicationFiled: November 19, 2020Publication date: May 19, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Inpil YOO, JooYang EOM
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Patent number: 11296069Abstract: In one general aspect, a device can include a leadframe including at least one of an external input terminal or an external output terminal, an interposer made of an insulating material, and a redistribution layer coupled to the interposer and made of a conductive material. The redistribution layer can include a plurality of traces. The device can also include a semiconductor die disposed between the redistribution layer and the leadframe.Type: GrantFiled: January 8, 2020Date of Patent: April 5, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Elsie Agdon Cabahug, Marie Clemens Ypil Quinones, Maria Cristina Estacio, Romel Nogas Manatad, Chung-Lin Wu, Jerome Teysseyre
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Patent number: 11264311Abstract: Implementations of a clip may include a first copper layer directly bonded to a first side of a ceramic layer, a second copper layer directly bonded to a second side of the ceramic layer, the second side of the ceramic layer opposite the first side of the ceramic layer, and a plurality of channels partially etched into a thickness of the second copper layer.Type: GrantFiled: November 7, 2019Date of Patent: March 1, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Inpil Yoo, Seungwon Im, JooYang Eom, Jerome Teysseyre
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Publication number: 20220059443Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first contact pad of the leadframe. The second terminal of the inductor can be electrically coupled with the leadframe via a second contact pad of the leadframe. The first contact pad and the second contact pad can be exposed through a molding compound by respective mold cavities defined in the molding compound. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: ApplicationFiled: November 4, 2021Publication date: February 24, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina ESTACIO
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Patent number: 11231386Abstract: A compact microelectronic gas sensor module includes electrical contacts formed in such a way that they do not consume real estate on an integrated circuit chip. Using such a design, the package can be miniaturized further. The gas sensor is packaged together with a custom-designed Application Specific Integrated Circuit (ASIC) that provides circuitry for processing sensor signals to identify gas species within a sample under test. In one example, the output signal strength of the sensor is enhanced by providing an additional metal surface area in the form of pillars exposed to an electrolytic gas sensing compound, while reducing the overall package size. In some examples, bottom side contacts are formed on the underside of the substrate on which the gas sensor is formed. Sensor electrodes may be electrically coupled to the ASIC directly, or indirectly by vias.Type: GrantFiled: November 14, 2017Date of Patent: January 25, 2022Assignee: STMicroelectronics Pte LtdInventors: Jerome Teysseyre, Yonggang Jin, Suman Cherian
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Publication number: 20220020740Abstract: Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.Type: ApplicationFiled: October 1, 2020Publication date: January 20, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tiburcio A. MALDO, Keunhyuk LEE, Jerome TEYSSEYRE
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Patent number: 11222832Abstract: In a general aspect, an apparatus can include a leadframe. The apparatus can also include a first semiconductor die coupled with a first side of a first portion of the leadframe, and a second semiconductor die coupled with a second side of the first portion of the leadframe. The apparatus can also include a first substrate coupled with a second side of the first semiconductor die. The first substrate can be further coupled with a first side of a second portion of the leadframe and a first side of a third portion of the leadframe. The apparatus can also further include a second substrate coupled with a second side of the second semiconductor die. The second substrate can be further coupled with a second side of the second portion of the leadframe and a second side of the third portion of the leadframe.Type: GrantFiled: July 16, 2019Date of Patent: January 11, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tiburcio Maldo, Keunhyuk Lee, Jerome Teysseyre
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Patent number: 11177203Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.Type: GrantFiled: February 19, 2019Date of Patent: November 16, 2021Assignee: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio