Patents by Inventor Jerome Teysseyre

Jerome Teysseyre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190391264
    Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.
    Type: Application
    Filed: September 5, 2019
    Publication date: December 26, 2019
    Inventors: Jing-En LUAN, Jerome TEYSSEYRE
  • Publication number: 20190341332
    Abstract: A dual-side cooling package includes a first semiconductor die and a second semiconductor die disposed between a first direct bonded metal (DBM) substrate and a second DBM substrate. A metal surface of the first DBM substrate defines a first outer surface of a package and a metal surface of the second DBM substrate defines a second outer surface of the package. The first semiconductor die is thermally coupled to the first DBM substrate. A first conductive spacer thermally couples the first semiconductor die to the second DBM substrate. The second semiconductor die is thermally coupled to a second conductive spacer. Further, one of the second semiconductor die and the second conductive spacer is thermally coupled to the first DMB substrate and the other of the second semiconductor die and the second conductive spacer is thermally coupled to the second DBM substrate.
    Type: Application
    Filed: January 9, 2019
    Publication date: November 7, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Yusheng LIN, Jerome TEYSSEYRE
  • Publication number: 20190341327
    Abstract: In one general aspect, an apparatus can include a module including a semiconductor die. The apparatus can include a heatsink coupled to the module and including a substrate, and a plurality of protrusions. The apparatus can include a cover including a channel where the plurality of protrusions of the heatsink are disposed within the channel, and can include a sealing mechanism disposed between the cover and the module.
    Type: Application
    Filed: May 1, 2018
    Publication date: November 7, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jerome TEYSSEYRE, Roveendra PAUL, Dukyong LEE
  • Patent number: 10429509
    Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 1, 2019
    Assignee: STMICROELECTRONICS PTE LTD.
    Inventors: Jing-En Luan, Jerome Teysseyre
  • Publication number: 20190287886
    Abstract: In a general aspect, a method can include forming a first conductive metal layer including a common gate conductor, and coupling a plurality of semiconductor die to the common gate conductor of the first conductive metal layer where the plurality of semiconductor die include a first silicon carbide die and a second silicon carbide die. The method can include encapsulating at least a portion of the first conductive metal layer and the semiconductor die within an insulator where the first conductive metal layer includes a first conductive path between the common gate conductor and a die gate conductor of the first silicon carbide die, and a second conductive path between the common gate conductor and a die gate conductor of the second silicon carbide die. The first conductive path can have a length substantially equal to a length of the second conductive path.
    Type: Application
    Filed: June 3, 2019
    Publication date: September 19, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jerome TEYSSEYRE, Maria Cristina ESTACIO, Seungwon IM
  • Publication number: 20190221493
    Abstract: In one general aspect, a package can include a first submodule including a first semiconductor die coupled to a first substrate and a first spacer, and disposed between the first spacer and the first substrate. The first submodule includes a second spacer disposed lateral to the first semiconductor die. The package includes a second submodule including a second semiconductor die coupled to a second substrate and a third spacer, and disposed between the third spacer and the second substrate. The second submodule includes a fourth spacer disposed lateral to the second semiconductor die. The package includes an inter-module layer disposed between the first submodule and the second submodule. The first spacer of the first submodule is electrically coupled to the fourth spacer of the second-submodule via the inter-module layer. The second spacer of the first submodule is electrically coupled to the third spacer of the second-submodule via the inter-module layer.
    Type: Application
    Filed: January 18, 2018
    Publication date: July 18, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jie CHANG, HuiBin CHEN, Keunhyuk LEE, Jerome TEYSSEYRE
  • Publication number: 20190181083
    Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate, the assembly being mounted on the leadframe and an inductor having a first terminal and a second terminal. The first terminal of the inductor can be electrically coupled with the leadframe via a first conductive clip, where the first terminal of the inductor can be coupled with a contact pad of the first conductive clip. The second terminal of the inductor can be electrically coupled with the leadframe via a second conductive clip, where the second terminal of the inductor can be coupled with a contact pad of the second conductive clip. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.
    Type: Application
    Filed: February 19, 2019
    Publication date: June 13, 2019
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina ESTACIO
  • Patent number: 10319670
    Abstract: In a general aspect, an apparatus can include a package including a common gate conductor, a first silicon carbide die having a die gate conductor, and a second silicon carbide die having a die gate conductor. The apparatus can include a first conductive path between the common gate conductor and the die gate conductor of the first silicon carbide die and a second conductive path between the common gate conductor and the die gate conductor of the second silicon carbide die where the first conductive path has a length substantially equal to a length of the second conductive path.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: June 11, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jerome Teysseyre, Maria Cristina Estacio, Seungwon Im
  • Publication number: 20190122970
    Abstract: In a general aspect, an apparatus can include a package including a common gate conductor, a first silicon carbide die having a die gate conductor, and a second silicon carbide die having a die gate conductor. The apparatus can include a first conductive path between the common gate conductor and the die gate conductor of the first silicon carbide die and a second conductive path between the common gate conductor and the die gate conductor of the second silicon carbide die where the first conductive path has a length substantially equal to a length of the second conductive path.
    Type: Application
    Filed: October 20, 2017
    Publication date: April 25, 2019
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jerome TEYSSEYRE, Maria Cristina ESTACIO, Seungwon IM
  • Patent number: 10256178
    Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: April 9, 2019
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Jerome Teysseyre, Romel Manatad, Chung-Lin Wu, Bigildis Dosdos, Erwin Ian Almagro, Maria Cristina Estacio
  • Patent number: 10128207
    Abstract: One or more embodiments are directed to semiconductor packages that include a pillar and bump structures. The semiconductor packages include a die that has recess at a perimeter of the semiconductor die. The semiconductor package includes an encapsulation layer that is located over the semiconductor die filling the recess and surrounding side surfaces of the pillars. The package may be formed on a wafer with a plurality of die and may be singulated into a plurality of packages.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: November 13, 2018
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Yun Liu, Jerome Teysseyre, Yonggang Jin
  • Publication number: 20180068935
    Abstract: In a general aspect, an apparatus can include a leadframe including a plurality of leads configured to be coupled with a printed circuit board. The plurality of leads can be disposed along a single edge of the apparatus. The apparatus can also include an assembly including a substrate and a plurality of semiconductor die disposed on the substrate. The assembly can being mounted on the leadframe. The apparatus can further include an inductor having a first terminal and a second terminal. The first terminal of the inductor can being coupled with the leadframe via a first contact pad, and the second terminal of the inductor can be coupled with the leadframe via a second contact pad. The leadframe, the assembly and the inductor can be arranged in a stacked configuration.
    Type: Application
    Filed: August 31, 2017
    Publication date: March 8, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Jerome TEYSSEYRE, Romel MANATAD, Chung-Lin WU, Bigildis DOSDOS, Erwin Ian ALMAGRO, Maria Cristina Estacio
  • Publication number: 20180067074
    Abstract: A compact microelectronic gas sensor module includes electrical contacts formed in such a way that they do not consume real estate on an integrated circuit chip. Using such a design, the package can be miniaturized further. The gas sensor is packaged together with a custom-designed Application Specific Integrated Circuit (ASIC) that provides circuitry for processing sensor signals to identify gas species within a sample under test. In one example, the output signal strength of the sensor is enhanced by providing an additional metal surface area in the form of pillars exposed to an electrolytic gas sensing compound, while reducing the overall package size. In some examples, bottom side contacts are formed on the underside of the substrate on which the gas sensor is formed. Sensor electrodes may be electrically coupled to the ASIC directly, or indirectly by vias.
    Type: Application
    Filed: November 14, 2017
    Publication date: March 8, 2018
    Inventors: Jerome Teysseyre, Yonggang Jin, Suman Cherian
  • Patent number: 9851328
    Abstract: A compact microelectronic gas sensor module includes electrical contacts formed in such a way that they do not consume real estate on an integrated circuit chip. Using such a design, the package can be miniaturized further. The gas sensor is packaged together with a custom-designed Application Specific Integrated Circuit (ASIC) that provides circuitry for processing sensor signals to identify gas species within a sample under test. In one example, the output signal strength of the sensor is enhanced by providing an additional metal surface area in the form of pillars exposed to an electrolytic gas sensing compound, while reducing the overall package size. In some examples, bottom side contacts are formed on the underside of the substrate on which the gas sensor is formed. Sensor electrodes may be electrically coupled to the ASIC directly, or indirectly by vias.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: December 26, 2017
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Jerome Teysseyre, Yonggang Jin, Suman Cherian
  • Publication number: 20160293559
    Abstract: One or more embodiments are directed to semiconductor packages that include a pillar and bump structures. The semiconductor packages include a die that has recess at a perimeter of the semiconductor die. The semiconductor package includes an encapsulation layer that is located over the semiconductor die filling the recess and surrounding side surfaces of the pillars. The package may be formed on a wafer with a plurality of die and may be singulated into a plurality of packages.
    Type: Application
    Filed: March 31, 2015
    Publication date: October 6, 2016
    Inventors: Yun Liu, Jerome Teysseyre, Yonggang Jin
  • Publication number: 20160284631
    Abstract: In one general aspect, a device can include a leadframe including at least one of an external input terminal or an external output terminal, an interposer made of an insulating material, and a redistribution layer coupled to the interposer and made of a conductive material. The redistribution layer can include a plurality of traces. The device can also include a semiconductor die disposed between the redistribution layer and the leadframe.
    Type: Application
    Filed: March 24, 2016
    Publication date: September 29, 2016
    Inventors: Elsie Agdon CABAHUG, Marie Clemens Ypil QUINONES, Maria Cristina ESTACIO, Romel Nogas MANATAD, Chung-Lin WU, Jerome TEYSSEYRE
  • Publication number: 20160187483
    Abstract: A proximity sensor includes a printed circuit board substrate, a semiconductor die, electrical connectors, a lens, a light emitting assembly, and an encapsulating layer. The semiconductor die is positioned over the printed circuit board substrate with its upper surface facing away from the printed circuit board substrate. Each of the electrical connectors is in electrical communication with a contact pad of the semiconductor die and a respective contact pad of the printed circuit board substrate. The lens is positioned over a sensor area of the semiconductor die. The light emitting assembly includes a light emitting device having a light emitting area, a lens positioned over the light emitting area, and contact pads facing the printed circuit board substrate. The encapsulating layer is positioned on the printed circuit board substrate, at least one of the electrical connectors, the semiconductor die, the lens, and the light emitting assembly.
    Type: Application
    Filed: March 31, 2015
    Publication date: June 30, 2016
    Inventors: Jing-En LUAN, Jerome TEYSSEYRE
  • Publication number: 20160047774
    Abstract: A compact microelectronic gas sensor module includes electrical contacts formed in such a way that they do not consume real estate on an integrated circuit chip. Using such a design, the package can be miniaturized further. The gas sensor is packaged together with a custom-designed Application Specific Integrated Circuit (ASIC) that provides circuitry for processing sensor signals to identify gas species within a sample under test. In one example, the output signal strength of the sensor is enhanced by providing an additional metal surface area in the form of pillars exposed to an electrolytic gas sensing compound, while reducing the overall package size. In some examples, bottom side contacts are formed on the underside of the substrate on which the gas sensor is formed. Sensor electrodes may be electrically coupled to the ASIC directly, or indirectly by vias.
    Type: Application
    Filed: August 18, 2014
    Publication date: February 18, 2016
    Inventors: Jerome Teysseyre, Yonggang Jin, Suman Cherian
  • Patent number: 9254596
    Abstract: A top-gate molding system for encapsulating semiconductor devices includes a plurality of mold cavities formed between a middle plate and a bottom plate, and a runner system formed between an upper plate and the middle plate. The runner system includes a runner with a plurality of reservoirs along its length, with a gate extending from each of the reservoirs to one of the cavities. A particle trap is positioned on the bottom of the runner between a sprue and a first one of the reservoirs, to capture contaminating particles in a flow of molding compound before the particles enter any of the reservoirs. The particle trap can be, for example, a notch or a channel extending transversely across the bottom of the runner, or a dummy reservoir upstream of the first of the plurality of reservoirs.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: February 9, 2016
    Assignee: STMICROELECTRONICS PTE LTD.
    Inventors: Jerome Teysseyre, Glenn de los Reyes
  • Patent number: 9059058
    Abstract: An image sensor device may include a bottom interconnect layer, an image sensing IC above the bottom interconnect layer and coupled thereto, and an adhesive material on the image sensing IC. The image sensor device may include an IR filter layer above the lens layer, and an encapsulation material on the bottom interconnect layer and surrounding the image sensing IC, the lens layer, and the IR filter layer. The image sensor device may include a top contact layer above the encapsulation material and including a dielectric layer, and a contact thereon, the dielectric layer being flush with adjacent portions of the IR filter layer.
    Type: Grant
    Filed: October 22, 2012
    Date of Patent: June 16, 2015
    Assignee: STMICROELECTRONICS PTE LTD
    Inventors: Jerome Teysseyre, Yonggang Jin