Patents by Inventor Jerry Lo
Jerry Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240118821Abstract: A data storage device processes a mixed workload including a plurality of superblocks to be written to and read from a plurality of memory dies, where each of the plurality of superblocks to be apportioned among the plurality of memory dies. The data storage device writes a first data stripe associated with a first superblock to the plurality of memory dies according to a sequential write pattern, and reads the first data stripe associated with the first superblock from the plurality of memory dies according to a sequential read pattern. The sequential write pattern causes the controller to write to the plurality of memory dies in a first order of memory dies. The sequential read pattern causes the controller to read from the plurality of memory dies in a second order of memory dies different from the first order of memory dies, thereby reducing read collisions.Type: ApplicationFiled: July 6, 2023Publication date: April 11, 2024Applicant: Western Digital Technologies, Inc.Inventors: Neil HUTCHISON, Haining LIU, Jerry LO, Sergey Anatolievich GOROBETS
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Patent number: 11543974Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: GrantFiled: January 20, 2021Date of Patent: January 3, 2023Assignee: Western Digital Technologies, Inc.Inventors: Jerry Lo, Dominic S. Suryabudi, Lan D. Phan
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Patent number: 11474709Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: January 20, 2021Date of Patent: October 18, 2022Assignee: Western Digital Technologies, Inc.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Patent number: 11048589Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: GrantFiled: April 17, 2019Date of Patent: June 29, 2021Assignee: Western Digital Technologies, Inc.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Publication number: 20210141543Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: ApplicationFiled: January 20, 2021Publication date: May 13, 2021Inventors: Jerry LO, Dominic S. SURYABUDI, Lan D. PHAN
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Publication number: 20210141542Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: ApplicationFiled: January 20, 2021Publication date: May 13, 2021Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Patent number: 10942656Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: GrantFiled: July 26, 2019Date of Patent: March 9, 2021Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Jerry Lo, Dominic S. Suryabudi, Lan D. Phan
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Patent number: 10901632Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: July 26, 2019Date of Patent: January 26, 2021Assignee: WESTERN DITIGAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Patent number: 10545810Abstract: Aspects of the disclosure provide a method and an apparatus that perform a background media scan (BGMS) with improved efficiency. In particular, the disclosed BGMS processes can monitor data retention performance of a large capacity solid state drive (SSD) without significantly increasing scanning overhead by scanning only some sample pages of a memory block.Type: GrantFiled: December 22, 2016Date of Patent: January 28, 2020Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard David Barndt, Hung-min Chang, Aldo Giovanni Cometti, Jerry Lo, Hung-Cheng Yeh
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Publication number: 20190347017Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Jerry LO, Dominic S. SURYABUDI, Lan D. PHAN
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Publication number: 20190347018Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: ApplicationFiled: July 26, 2019Publication date: November 14, 2019Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Publication number: 20190251028Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: ApplicationFiled: April 17, 2019Publication date: August 15, 2019Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Patent number: 10379758Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: GrantFiled: July 31, 2017Date of Patent: August 13, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Patent number: 10379755Abstract: A data storage subsystem is disclosed that implements a process for storing and/or reconstructing system data, such as a system mapping table. In certain embodiments, table pages are systematically copied, or flushed, to non-volatile memory in a progressive manner, according to a fixed ratio of flushed table pages per table update trigger, thereby facilitating write and/or load efficiency. Full or partial reconstruction of a table may be performed within a bounded number of operations based on the size of the table, the ratio implemented, and/or other characteristics.Type: GrantFiled: October 26, 2015Date of Patent: August 13, 2019Assignee: Western Digital Technologies, Inc.Inventors: Jerry Lo, Dominic S. Suryabudi, Lan D. Phan
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Patent number: 10372382Abstract: Aspects of the disclosure provide methods and apparatus that monitor and mitigate Read Disturb errors in non-volatile memory (NVM) devices such as NAND flash memories. The disclosed methods and apparatus determine which logical block addresses (LBAs) in the NVM device are frequently accessed by a host, rather than looking a physical address accesses. The potential Read Disturb errors may then be mitigated by triggering Read Disturb mitigation when the numbers of access of one or more of the frequently accessed LBAs exceeds a predefined number of accesses.Type: GrantFiled: December 29, 2016Date of Patent: August 6, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Parvaneh Alavi, Hung-min Chang, Haining Liu, Jerry Lo, Hung-Cheng Yeh
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Patent number: 10373695Abstract: Aspects of the disclosure provide methods and apparatus for handling Read Disturb and block errors in a non-volatile memory (NVM) device. An error level of both an aggressor page that causes Read Disturb errors and an error level of adjacent victim pages are obtained. The error level of the victim page is compared against a predetermined threshold error level to determine if the victim page is experiencing a high level of bit errors. If so, then the error level of the aggressor page is compared to the error level of the victim page to determine whether Read Disturb errors are actually occurring due to host reads of the aggressor page. By looking at both the aggressor and victim error levels, a more accurate determination of Read Disturb errors may be obtained, resulting in less unnecessary relocations of pages and blocks within an NVM for mitigating Read Disturb effects.Type: GrantFiled: December 30, 2016Date of Patent: August 6, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Richard David Barndt, Aldo Giovanni Cometti, Haining Liu, Jerry Lo
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Patent number: 10289551Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: GrantFiled: May 11, 2017Date of Patent: May 14, 2019Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Kai-Lung Cheng, Yun-Tzuo Lai, Eugene Lisitsyn, Jerry Lo, Subhash Balakrishna Pillai
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Publication number: 20180373445Abstract: The subject technology provides for managing a data storage system. A host write command to write host data associated with a logical address to a non-volatile memory is received. A first physical address in the non-volatile memory mapped to the logical address in an address mapping table is determined. An indicator that the first physical address is bad checked. If the first physical address is indicated as bad, a valid count associated with a first set of physical addresses at a current value is maintained. The first set of physical addresses comprises the first physical address. If the first physical address is not indicated as bad, the first physical address is marked as invalid. The valid count associated with the first set of physical addresses is decremented.Type: ApplicationFiled: July 31, 2017Publication date: December 27, 2018Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Publication number: 20180329818Abstract: Host data segments are received and stored in a cached data unit corresponding to a previously stored data unit currently stored in non-volatile memory. Metadata is created that identifies unmodified previously stored segments of host data in the previously stored data unit that correspond to the received host data segments, the metadata including an update flag indicating that the previously stored data unit requires updating. In response to detecting the unexpected interruption of power, the cached data unit and the metadata is written to an area of the non-volatile memory array that is different than where the previously stored data unit is currently stored. Upon resuming operation following the unexpected interruption of power, the cached data unit is identified based on the update flag, as having been saved in response to the power shutdown without the previously stored data unit being updated in the non-volatile memory array, and then reloaded into the memory cache.Type: ApplicationFiled: May 11, 2017Publication date: November 15, 2018Inventors: Kai-Lung CHENG, Yun-Tzuo LAI, Eugene LISITSYN, Jerry LO, Subhash Balakrishna PILLAI
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Publication number: 20180188981Abstract: Aspects of the disclosure provide methods and apparatus that monitor and mitigate Read Disturb errors in non-volatile memory (NVM) devices such as NAND flash memories. The disclosed methods and apparatus determine which logical block addresses (LBAs) in the NVM device are frequently accessed by a host, rather than looking a physical address accesses. The potential Read Disturb errors may then be mitigated by triggering Read Disturb mitigation when the numbers of access of one or more of the frequently accessed LBAs exceeds a predefined number of accesses.Type: ApplicationFiled: December 29, 2016Publication date: July 5, 2018Inventors: Parvaneh Alavi, Hung-min Chang, Haining Liu, Jerry Lo, Hung-Cheng Yeh