Patents by Inventor Jerry M. Brooks
Jerry M. Brooks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8115269Abstract: A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.Type: GrantFiled: February 22, 2010Date of Patent: February 14, 2012Assignee: Round Rock Research, LLCInventors: Warren M. Farnworth, Jerry M. Brooks
-
Patent number: 8049342Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: GrantFiled: July 27, 2009Date of Patent: November 1, 2011Assignee: Round Rock Research, LLCInventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 8048715Abstract: A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but within the second region. In one embodiment, in which semiconductor devices are to be stacked over and secured to the substrate in a flip-chip type arrangement, the contact areas correspond to bond pads of an upper, second semiconductor device, while other contact areas located within the first region correspond to bond pads of a lower, first semiconductor device. In another embodiment, the contact areas correspond to bond pads of the first semiconductor device, which are electrically connected thereto by way of laterally extending discrete conductive elements, while other contact areas that are located external to the second region correspond to bond pads of the upper, second semiconductor device.Type: GrantFiled: November 11, 2009Date of Patent: November 1, 2011Assignee: Round Rock Research, LLCInventors: David J. Corisis, Jerry M. Brooks, Matt E. Schwab
-
Patent number: 7999378Abstract: A semiconductor device assembly includes two or more dice stacked in laterally offset arrangement relative to one another. With such an arrangement, when a second semiconductor die is positioned over a first semiconductor die, bond pads of the first semiconductor die are exposed laterally beyond the second semiconductor die. The semiconductor dice of such an assembly may have similar dimensions and bond pad arrangements. In some embodiments the bond pads of each semiconductor die may be located on the active surface, along a single edge. The multiple chip device enables stacking of a plurality of semiconductor dice in a high density, low profile device.Type: GrantFiled: February 22, 2010Date of Patent: August 16, 2011Assignee: Round Rock Research, LLCInventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7998792Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangements, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high-density low-profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: GrantFiled: December 4, 2009Date of Patent: August 16, 2011Assignee: Round Rock Research, LLCInventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7944057Abstract: A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.Type: GrantFiled: December 4, 2009Date of Patent: May 17, 2011Assignee: Round Rock Research, LLCInventors: David J. Corisis, Jerry M. Brooks, Matt E. Schwab, Tracy V. Reynolds
-
Publication number: 20110101514Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradeable.Type: ApplicationFiled: January 12, 2011Publication date: May 5, 2011Inventors: Larry D. Kinsman, Jerry M. Brooks, Warren M. Farnworth, Walter L. Moden, Terry R. Lee
-
Patent number: 7871859Abstract: A vertically mountable semiconductor device assembly including a semiconductor device and a mechanism for attaching the semiconductor device to a carrier substrate. The semiconductor device has each of its bond pads disposed proximate a single edge thereof. Preferably, at least a portion of the semiconductor device is exposed. An alignment device is attached to a carrier substrate. A mounting element on the vertically mountable semiconductor device package engages the alignment device to interconnect the semiconductor device and the alignment device. Preferably, the alignment device secures the vertically mountable semiconductor device package perpendicular relative to the carrier substrate. The distance between the bond pads and corresponding terminals on the carrier substrate is very small in order to reduce impedance. The vertically mountable semiconductor device package may also be readily user-upgradable.Type: GrantFiled: July 23, 2002Date of Patent: January 18, 2011Assignee: Round Rock Research, LLCInventors: Larry D. Kinsman, Jerry M. Brooks, Warren M. Farnworth, Walter L. Moden, Terry R. Lee
-
Patent number: 7851922Abstract: A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.Type: GrantFiled: September 9, 2008Date of Patent: December 14, 2010Assignee: Round Rock Research, LLCInventors: David J. Corisis, Jerry M. Brooks, Matt E. Schwab, Tracy V. Reynolds
-
Publication number: 20100148331Abstract: A semiconductor device assembly includes two or more dice stacked in laterally offset arrangement relative to one another. With such an arrangement, when a second semiconductor die is positioned over a first semiconductor die, bond pads of the first semiconductor die are exposed laterally beyond the second semiconductor die. The semiconductor dice of such an assembly may have similar dimensions and bond pad arrangements. In some embodiments the bond pads of each semiconductor die may be located on the active surface, along a single edge. The multiple chip device enables stacking of a plurality of semiconductor dice in a high density, low profile device.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: ROUND ROCK RESEARCH, LLCInventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Publication number: 20100148372Abstract: A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.Type: ApplicationFiled: February 22, 2010Publication date: June 17, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Warren M. Farnworth, Jerry M. Brooks
-
Patent number: 7704794Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: GrantFiled: November 13, 2006Date of Patent: April 27, 2010Assignee: Micron Technology, Inc.Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Publication number: 20100078793Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangements, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high-density low-profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: ApplicationFiled: December 4, 2009Publication date: April 1, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Publication number: 20100078792Abstract: A rerouting element for a semiconductor device includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.Type: ApplicationFiled: December 4, 2009Publication date: April 1, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: David J. Corisis, Jerry M. Brooks, Matt E. Schwab, Tracy V. Reynolds
-
Patent number: 7674652Abstract: A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.Type: GrantFiled: September 1, 2005Date of Patent: March 9, 2010Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Jerry M. Brooks
-
Publication number: 20100055837Abstract: A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but within the second region. In one embodiment, in which semiconductor devices are to be stacked over and secured to the substrate in a flip-chip type arrangement, the contact areas correspond to bond pads of an upper, second semiconductor device, while other contact areas located within the first region correspond to bond pads of a lower, first semiconductor device. In another embodiment, the contact areas correspond to bond pads of the first semiconductor device, which are electrically connected thereto by way of laterally extending discrete conductive elements, while other contact areas that are located external to the second region correspond to bond pads of the upper, second semiconductor device.Type: ApplicationFiled: November 11, 2009Publication date: March 4, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: David J. Corisis, Jerry M. Brooks, Matt E. Schwab
-
Publication number: 20090286356Abstract: A semiconductor device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a high density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.Type: ApplicationFiled: July 27, 2009Publication date: November 19, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
-
Patent number: 7619313Abstract: A substrate includes first and second regions over which first and second semiconductor devices are to be respectively positioned. The first region is located at least partially within the second region. Contact areas are located external to the first region but within the second region. In one embodiment, in which semiconductor devices are to be stacked over and secured to the substrate in a flip-chip type arrangement, the contact areas correspond to bond pads of an upper, second semiconductor device, while other contact areas located within the first region correspond to bond pads of a lower, first semiconductor device. In another embodiment, the contact areas correspond to bond pads of the first semiconductor device, which are electrically connected thereto by way of laterally extending discrete conductive elements, while other contact areas that are located external to the second region correspond to bond pads of the upper, second semiconductor device.Type: GrantFiled: August 1, 2006Date of Patent: November 17, 2009Assignee: Micron Technology, Inc.Inventors: David J. Corisis, Jerry M. Brooks, Matt E. Schwab
-
Publication number: 20090008797Abstract: A rerouting element for a semiconductor device that includes a dielectric film that carries conductive vias, conductive elements, and contact pads. The conductive vias are positioned at locations that correspond to the locations of bond pads of a semiconductor device with which the rerouting element is to be used. The conductive elements, which communicate with corresponding conductive vias, reroute the bond pad locations to corresponding contact pad locations adjacent to one peripheral edge or two adjacent peripheral edges of the rerouted semiconductor device. The rerouting element is particularly useful for rerouting centrally located bond pads of a semiconductor device, as well as for rerouting the peripheral locations of bond pads of a semiconductor device to one or two adjacent peripheral edges thereof. Methods for designing and using the rerouting element are also disclosed, as are semiconductor device assemblies including one or more rerouting elements.Type: ApplicationFiled: September 9, 2008Publication date: January 8, 2009Applicant: MICRON TECHNOLOGY, INC.Inventors: David J. Corisis, Jerry M. Brooks, Matt E. Schwab, Tracy V. Reynolds
-
Patent number: RE43112Abstract: A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.Type: GrantFiled: May 18, 2006Date of Patent: January 17, 2012Assignee: Round Rock Research, LLCInventors: David J. Corisis, Jerry M. Brooks, Walter L. Moden