Stackable ball grid array package
A stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of an integrated circuit (IC) device mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device, including the wiring interconnect and encapsulate material, as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires are used to attach the IC device to the printed board substrate and encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.
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More than one reissue application has been filed for the reissue of U.S. Pat. No. 6,738,263. The reissue applications are U.S. application Ser. No. 09/944,512, filed Aug. 30, 2001, now U.S. Pat. No. 6,549,421, issued Apr. 15, 2003, which is a continuation of U.S. application Ser. No. 09/416,249, filed Oct. 12, 1999, now U.S. Pat. No. 6,331,939, issued Dec. 18, 2001, which is a divisional of U.S. application Ser. No. 09/072,101, filed May 4, 1998, now U.S. Pat. No. 6,072,233, issued Jun. 6, 2000.
CROSS-REFERENCE TO RELATED APPLICATIONSThis application is a continuation reissue application of U.S. application Ser. No. 10/222,243, filed Aug. 16, 2002, now U.S. Pat. No. 6,738,263, issued May 18, 2004, which is a continuation of U.S. application Ser. No. 09/944,512, filed Aug. 30, 2001, pending now U.S. Pat. No. 6,549,421, issued Apr. 15, 2003, which is a continuation of U.S. application Ser. No. 09/416,249, filed Oct. 12, 1999, now U.S. Pat. No. 6,331,939, issued Dec. 18, 2001, which is a divisional of U.S. application Ser. No. 09/072,101, filed May 4, 1998, now U.S. Pat. No. 6,072,233, issued Jun. 6, 2000.
BACKGROUND OF THE INVENTIONThe present invention relates generally to packaging semiconductor devices and, more particularly, the present invention relates to fine ball grid array packages that can be stacked to form highly dense components.
Ball grid array (BGA) semiconductor packages are well known in the art. BGA packages typically comprise a substrate, such as a printed circuit board, with a semiconductor die mounted on the top side of the substrate. The semiconductor die has a multitude of bond pads electrically connected to a series of metal traces on the top side of the printed circuit board. The connection between the bond pads and the metal traces is provided by wire bonds electrically and mechanically connected between the two. This series of metal traces is connected to a second series of metal traces on the underside of the printed circuit board through a series of vias. The second series of metal traces each terminate with a connect contact pad where a conductive element is attached. The conductive elements can be solder balls or conductive filled epoxy. The conductive elements are arranged in an array pattern and the semiconductor die and wire bonds are encapsulated with a molding compound.
As chip and grid array densities increase, the desire in packaging semiconductor chips has been to reduce the overall height or profile of the semiconductor package. The use of BGAs has allowed for this reduction of profile as well as increased package density. Density reduction has been achieved by utilizing lead frames, such as lead-over chips, in order to increase the densities as well as to branch out into being able to stack units one on top another.
One example of a lead chip design in a BGA package is shown in U.S. Pat. No. 5,668,405, issued Sep. 16, 1997. This patent discloses a semiconductor device that has a lead frame attached to the semiconductor chip. Through holes are provided that allow for solder bumps to connect via the lead frame to the semiconductor device. This particular reference requires several steps of attaching the semiconductor device to the lead frame, then providing sealing resin, and then adding a base film and forming through holes in the base film. A cover resin is added before solder bumps are added in the through holes to connect to the lead frame. This particular structure lacks the ability to stack devices one on top another.
U.S. Pat. No. 5,677,566, issued Oct. 14, 1997, and commonly assigned to the assignee of the present invention, discloses a semiconductor chip package that includes discrete conductive leads with electrical contact bond pads on a semiconductor chip. The lead assembly is encapsulated with a typical encapsulating material and electrode bumps are formed through the encapsulating material to contact the conductive leads. The electrode bumps protrude from the encapsulating material for connection to an external circuit. The semiconductor chip has the bond leads located in the center of the die, thus allowing the conductive leads to be more readily protected once encapsulated in the encapsulating material. Unfortunately, this particular assembly taught in the '566 patent reference also lacks the ability to stack one semiconductor device on top another.
Attempts have been made to stack semiconductor devices in three dimensional integrated circuit packages. One such design is disclosed in U.S. Pat. No. 5,625,221, issued Apr. 29, 1997. This patent discloses a semiconductor package assembly that has recessed edge portions that extend along at least one edge portion of the assembly. An upper surface lead is exposed therefrom and a top recess portion is disposed on a top surface of the assembly. A bottom recess portion is disposed on the bottom surface of the assembly such that when the assembly is used in fabricating a three-dimensional integrated circuit module, the recessed edge portion accommodates leads belonging to an upper semiconductor assembly to provide electrical interconnection therebetween. Unfortunately, the assembly requires long lead wires from the semiconductor chip to the outer edges. These lead wires add harmful inductance and unnecessary signal delay and can form a weak link in the electrical interconnection between the semiconductor device and the outer edges. Further, the device profile is a sum of the height of the semiconductor die, the printed circuit board to which it is bonded, the conductive elements, such as the solder balls, and the encapsulant that must cover the die and any wire bonds used to connect the die to the printed circuit board. So, reducing the overall profile is difficult because of the geometries required in having the lead pads on the semiconductor chip along the outer periphery with extended lead wires reaching from the chip to the outer edges.
Another stacked arrangement of semiconductor devices on a substrate interconnected by pins is illustrated in U.S. Pat. Nos. 5,266,912 and 5,400,003. However, the height of the stacked package is limited by the length of the pin connections between the individual multi-chip modules or printed circuit boards.
Accordingly, what is needed is a ball grid array package that allows stacking of packages on one another. This stackable package would have a lower profile than otherwise provided in the prior art and would reduce the number of steps in the assembly of the package.
SUMMARY OF THE INVENTIONAccording to the present invention, a stackable fine ball grid array (FBGA) package is disclosed that allows the stacking of one array upon another. This stackable FBGA package is configured such that conductive elements are placed along the outside perimeter of a semiconductor device (integrated circuit (IC) device) mounted to the FBGA. The conductive elements also are of sufficient size so that they extend beyond the bottom or top surface of the IC device. Wire interconnect connects the IC device in a way that does not increase the overall profile of the package. Encapsulating material protects both the IC device and the wire interconnect as the conductive elements make contact with the FBGA positioned below or above to form a stack. The IC device, such as a memory chip, is mounted upon a first surface of a printed circuit board substrate forming part of the FBGA. Lead wires, or wire interconnect, are used to attach the IC device to the printed circuit board substrate and an encapsulant is used to contain the IC device and wires within and below the matrix and profile of the conductive elements.
Additionally, certain pins on the FBGA in the stack require an isolated connection to the PC board. An example of such a requirement is when an activation signal for a particular IC device within the stack must be sent solely to that device and not to any of the other devices within the stack. This isolated connection connects to an adjacent ball on a different FBGA stack above or below that particular isolated connection since in common pin layouts of the devices are stacked together, and each device requires an isolated connection to the PC board. This provides for a stair step connection from the bottom of the FBGA stacked array to the top that allows each device, from the bottom one to the top one, to have an isolated connection from each other. This allows IC devices to be stacked one upon the other while maintaining a unique pin out for each pin required in the stack.
Further, the FBGA of the present invention keeps the wire lengths between the IC device and the conductors of the PC board to a minimum for the control of the impedance of the conductors.
Referring to drawing
FBGA package 10 further comprises an integrated circuit or semiconductor die 14 attached to a die attach pad 16 formed on the upper surface of substrate 12. Semiconductor die 14 is attached to die attach pad 16 using a dielectric adhesive that is nonconductive and has a thermal coefficient of expansion (TCE) that closely matches that of the semiconductor die 14. The adhesive can be any type of epoxy resin or other polymer adhesives typically used for such purposes. Alternately, the die attach pad 16 may be formed of double sided, adhesively coated tape, such as an adhesively coated Kapton™ tape or the like. The semiconductor die 14 is formed having a plurality of bond pads 18 that is formed on the active surface thereof which mates with die attach pad 16 of the substrate 12. Each bond pad of the plurality of bond pads 18 aligns with a corresponding aperture 24 in substrate 12. Each bond pad of the plurality of bond pads 18 is electrically connected to terminal pads 20 that are on the surface of substrate 12. Wire bonds 22 are used to form the connections between the plurality of bond pads 18 on the semiconductor die 14 and the terminal pads 20 of the substrate 12 wherein the wire bonds 22 pass through an aperture 24 formed in the substrate 12. A portion of semiconductor die 14 where the bond pads 18 are located, along with the cavity formed by aperture 24, is covered by an encapsulating material 26. Encapsulating material 26 covers or seals bond pads 18, terminal pads 20, and wire bonds 22 to protect them from dust, moisture, and any incidental contact. The encapsulating material 26 has a second height, the second height being less than the first height of the conductive elements 28.
Conductive elements 28 are attached or bonded to conductive traces 30 (see
Next, as illustrated in drawing
Depicted in drawing
Referring to drawing
A third embodiment of the present invention is depicted in drawing
Referring to drawing
Referring to drawing
Referring to drawing
Referring to drawing
Referring to drawing
There has been shown and described a novel semiconductor chip package that is stackable and has a lower profile over that of the prior art. The particular embodiments shown in the drawings and described herein are for purposes of example and are not to be construed to limit the invention as set forth in the pending claims. Those skilled in the art may know numerous uses and modifications of the specific embodiments described without departing from the scope of the invention. The process steps described may, in some instances, be formed in a different order or equivalent structures and processes may be substituted for various structures and processes described.
Claims
1. A computer system having an input device, an output device, a processor connected to said input device and said output device, and a memory connected to said processor, comprising:
- said memory comprising a memory module connected to said processor, said memory module including: a ball grid array, comprising: a printed circuit board substrate having a first surface, a second surface, and an aperture, said first surface including a plurality of conductive element pads, at least one conductive element pad on said second surface and at least one terminal pad on said second surface; a memory semiconductor device-mounted within a first perimeter of said first surface of said printed circuit board substrate and having at least one bond pad; at least one wire bond connected to said at least one bond pad on said memory semiconductor device and said at least one terminal pad on said second surface of said printed circuit board substrate while passing through said aperture; a material placed along said aperture, on said at least one bond pad, said at least one terminal pad, and said at least one wire bond, forming a first profile height; and a plurality of conductive elements, mounted along a second perimeter of said second surface, said second perimeter being greater than said first perimeter, and coupled to said at least one conductive element pad on said second surface, said plurality of conductive elements having a second profile height greater than said first profile height.
2. The computer system according to claim 1, wherein a first part of each conductive element of said plurality of conductive elements aligns in a first parallel row having a first pitch spacing.
3. The computer system according to claim 2, wherein a second part of each conductive element of said plurality of conductive elements aligns in a second parallel row having a second pitch spacing.
4. The computer system according to claim 1, wherein said material has a second profile height less than said first profile height.
5. The computer system according to claim 1, wherein said at least one conductive element pad is connected to said at least one bond pad through said printed circuit board substrate.
6. The computer system according to claim 1, wherein at least one conductive element of said plurality of conductive elements is isolated.
7. A method of forming a stacked semiconductor assembly, comprising:
- providing a plurality of semiconductor substrates each having a first surface, a second surface, at least one aperture, a plurality of terminal pads on the second surface adjacent the at least one aperture, the terminal pads coupled to conductive element pads on the second surface by conductive traces on the second surface, and a plurality of conductive element pads on the second surface;
- mounting a respective semiconductor die having a perimeter on the first surface of each of the semiconductor substrates, the semiconductor dies having bond pads on a front surface disposed on the first surface of the respective substrates, the bond pads overlying the at least one aperture in the respective substrates;
- connecting at least one bond pad of each of the semiconductor dies to at least one of the conductive element pads on the second surface of the respective substrate by connecting one end of a bond wire to a bond pad, extending the bond wire through the at least one aperture, and connecting the opposite end of the bond wire to one of the terminal pads on the second surface on the respective substrates;
- covering the bond wires and the portion of the semiconductor dies overlying the at least one aperture of each substrate with an encapsulant material, the encapsulant material being disposed in the aperture and projecting beyond the second surface of the respective semiconductor substrate at a first profile height;
- providing a plurality of conductive elements mounted on the conductive element pads on the second surface of each substrate, the conductive element pads forming a second perimeter on the substrate that is greater than a first perimeter, the conductive elements having a second profile height with respect to the second surface of the respective substrate that is greater than the first profile height, wherein the encapsulant material at the first profile height projects beyond the second surface of the semiconductor substrate such that the encapsulant material is substantially colinear with pairs of the conductive elements that are aligned with a central portion of the second perimeter; and
- aligning each of the semiconductor substrates in the plurality and positioning the substrates one atop the other such that the conductive elements mounted on the second surface of a first semiconductor substrate of the plurality aligns with and couples to the conductive element pads on the first surface of a second semiconductor substrate of the plurality of substrates, to form a vertically stacked assembly.
8. The method of forming the stacked semiconductor assembly of claim 7, wherein providing a plurality of conductive elements further comprises providing solder balls.
9. The method of forming the stacked semiconductor assembly of claim 7, wherein mounting a semiconductor die further comprises forming a die attach pad on the first surface of each of the plurality of semiconductor substrates for receiving the respective semiconductor die.
10. The method of claim 9, wherein forming a die attach pad further comprises forming an epoxy layer that is a dielectric.
11. The method of claim 9, wherein forming a die attach pad further comprises forming a layer of adhesive and tape wherein the tape is a dielectric.
12. The method of claim 11, wherein providing the tape further comprises providing a tape with an aperture that aligns with the aperture in the substrate.
13. The method of claim 7, wherein mounting the semiconductor dies further comprises providing, for at least one of the semiconductor dies, a memory device.
14. The method of claim 13, wherein mounting the semiconductor dies comprises mounting at least one dynamic memory device.
15. The method of claim 13, wherein mounting a semiconductor die comprises mounting at least one EPROM device.
16. The method of claim 15, wherein mounting an EPROM device comprises mounting a FLASH device.
17. The method of claim 7, wherein mounting the semiconductor dies comprises providing a memory device for each of the semiconductor dies.
18. The method of claim 7, wherein mounting the semiconductor dies further comprises providing semiconductor dies having bond pads located in the center portion.
19. The method of claim 18, wherein providing the substrates with an aperture comprises providing a substrate with a centrally located aperture.
20. The method of claim 7, wherein providing the substrates with an aperture comprises providing a substrate with a centrally located aperture.
21. A method of forming a substrate for use in a stacked semiconductor ball grid array assembly, comprising:
- providing a substrate having a first surface, a second surface, and an aperture, providing a plurality of conductive element pads on the first and second surfaces, providing terminal pads located adjacent the aperture on the second surface, providing conductive traces located on the second surface and electrically coupled to at least one of the terminal pads and to at least one of the conductive elements pads, and providing conductive vias extending through the substrate and coupling at least one of the conductive element pads on the first surface to at least one of the conductive element pads on the second surface;
- disposing a semiconductor die on the first surface of the substrate, the semiconductor die having a perimeter that is less than the perimeter on the first surface, the semiconductor die having bond pads that are placed over the aperture;
- disposing conductive elements on a perimeter on at least some of the conductive element pads on the second surface and electrically coupling these conductive elements to at least some of the conductive element pads on the first surface through the conductive vias, the conductive elements having a conductive element profile height with respect to the second surface;
- connecting the bond pads of the semiconductor die to at least one of the terminal pads on the second surface of the substrate by connecting a first end of a bond wire to at least one of the bond pads, extending the bond wire through the aperture, and coupling a second end of the bond wire to at least one of the terminal pads; and
- disposing encapsulant material over the second surface of the substrate and in the aperture such that the encapsulant material covers the bond wires and a portion of the semiconductor die exposed by the aperture, the encapsulant material projecting beyond the second surface of the substrate at an encapsulant profile height, wherein the encapsulant profile height is less than the conductive element profile height,
- wherein the encapsulant material projects beyond the second surface such that the encapsulant material is substantially colinear with pairs of the conductive elements that are aligned with a central portion of the second perimeter.
22. The method of claim 21, and further comprising disposing conductive elements forming a perimeter on the conductive element pads on the second surface and electrically coupling to at least one of the terminal pads on the second surface via the conductive traces on the second surface, the conductive elements having a conductive element profile height.
23. The method of claim 21, and further comprising providing a die attach pad of dielectric material on the first surface of the substrate and located within the perimeter, the die attach pad for receiving a semiconductor device with bond pads to be placed over the aperture in the substrate, the die attach pad having an opening that aligns with the aperture in the substrate.
24. The method of claim 21, wherein disposing conductive elements further comprises forming solder balls on the conductive element pads.
25. The method of claim 21, and further comprising providing additional conductive element pads on the second surface which are coupled to conductive element pads on the first surface, by forming conductive traces on each surface and coupling the traces to conductive vias through the substrate, wherein at least some of these additional conductive element pads provide an electrically isolated path coupling a conductive element pad on the first surface to a conductive element pad on the second surface that is electrically isolated from any terminal pads on the substrate.
26. The method of claim 21, wherein disposing the die on the first surface of the substrate further comprises forming a die attach pad on the substrate for receiving the semiconductor die having a thickness and mounting a semiconductor die on the die attach, the semiconductor die having a thickness, the combined thicknesses of the semiconductor die and the die attach pad forming a height with respect to the first surface of the substrate that is less than the conductive element profile height.
3648131 | March 1972 | Stuby |
4199777 | April 22, 1980 | Maruyama et al. |
4371912 | February 1, 1983 | Guzik |
4446477 | May 1, 1984 | Currie et al. |
4483067 | November 20, 1984 | Parmentier |
4505799 | March 19, 1985 | Baxter |
4638348 | January 20, 1987 | Brown et al. |
4649418 | March 10, 1987 | Uden |
4725924 | February 16, 1988 | Juan |
4731645 | March 15, 1988 | Parmentier et al. |
4761681 | August 2, 1988 | Reid |
4829666 | May 16, 1989 | Haghiri-Tehrani |
4841355 | June 20, 1989 | Parks |
4868712 | September 19, 1989 | Woodman |
4899107 | February 6, 1990 | Corbett et al. |
4931853 | June 5, 1990 | Ohuchi et al. |
4954458 | September 4, 1990 | Reid |
4956694 | September 11, 1990 | Eide |
4975765 | December 4, 1990 | Ackermann et al. |
4992849 | February 12, 1991 | Corbett et al. |
4992850 | February 12, 1991 | Corbett et al. |
4996587 | February 26, 1991 | Hinrichsmeyer et al. |
5012323 | April 30, 1991 | Farnworth |
5022580 | June 11, 1991 | Pedder |
5041396 | August 20, 1991 | Valero |
5043794 | August 27, 1991 | Tai et al. |
5048179 | September 17, 1991 | Shindo et al. |
5063177 | November 5, 1991 | Geller et al. |
5068205 | November 26, 1991 | Baxter et al. |
5075253 | December 24, 1991 | Sliwa et al. |
5086018 | February 4, 1992 | Conru et al. |
5099309 | March 24, 1992 | Kryzaniwsky |
5107328 | April 21, 1992 | Kinsman et al. |
5107329 | April 21, 1992 | Okinaga et al. |
5128831 | July 7, 1992 | Fox, III et al. |
5138434 | August 11, 1992 | Wood et al. |
5155067 | October 13, 1992 | Wood et al. |
5188984 | February 23, 1993 | Nishiguchi |
5191511 | March 2, 1993 | Sawaya |
5200363 | April 6, 1993 | Schmidt |
5216278 | June 1, 1993 | Lin et al. |
5218234 | June 8, 1993 | Thompson et al. |
5222014 | June 22, 1993 | Lin |
5231304 | July 27, 1993 | Solomon |
5239198 | August 24, 1993 | Lin et al. |
5239447 | August 24, 1993 | Cotues et al. |
5258330 | November 2, 1993 | Khandros et al. |
5266912 | November 30, 1993 | Kledzik |
5286679 | February 15, 1994 | Farnworth et al. |
5291062 | March 1, 1994 | Higgins, III |
5293068 | March 8, 1994 | Kohno et al. |
5294750 | March 15, 1994 | Sakai et al. |
5299092 | March 29, 1994 | Yaguchi et al. |
5311401 | May 10, 1994 | Gates, Jr. et al. |
5313096 | May 17, 1994 | Eide |
5326428 | July 5, 1994 | Farnworth et al. |
5343106 | August 30, 1994 | Lungu et al. |
5346859 | September 13, 1994 | Niwayama |
5346861 | September 13, 1994 | Khandros et al. |
5360942 | November 1, 1994 | Hoffman et al. |
5373189 | December 13, 1994 | Massit et al. |
5384689 | January 24, 1995 | Shen |
5397917 | March 14, 1995 | Ommen et al. |
5397921 | March 14, 1995 | Karnezos |
5400003 | March 21, 1995 | Kledzik |
5409865 | April 25, 1995 | Karnezos |
5419807 | May 30, 1995 | Akram et al. |
5420460 | May 30, 1995 | Massingill |
5422514 | June 6, 1995 | Griswold et al. |
5426072 | June 20, 1995 | Finnila |
5434106 | July 18, 1995 | Lim et al. |
5434452 | July 18, 1995 | Higgins |
5454161 | October 3, 1995 | Beilin et al. |
5468999 | November 21, 1995 | Lin |
5473512 | December 5, 1995 | Degani et al. |
5474957 | December 12, 1995 | Urushima |
5486723 | January 23, 1996 | Ma et al. |
5489804 | February 6, 1996 | Pasch |
5508556 | April 16, 1996 | Lin |
5528080 | June 18, 1996 | Goldstein |
5536685 | July 16, 1996 | Burward-Hoy |
5541450 | July 30, 1996 | Jones et al. |
5545291 | August 13, 1996 | Smith et al. |
5578525 | November 26, 1996 | Mizukoshi |
5578869 | November 26, 1996 | Hoffman et al. |
5608265 | March 4, 1997 | Kitano et al. |
5615089 | March 25, 1997 | Yoneda et al. |
5616958 | April 1, 1997 | Laine et al. |
5625221 | April 29, 1997 | Kim et al. |
5625227 | April 29, 1997 | Estes et al. |
5636104 | June 3, 1997 | Oh |
5637536 | June 10, 1997 | Val |
5637915 | June 10, 1997 | Sato et al. |
5639695 | June 17, 1997 | Jones et al. |
5639696 | June 17, 1997 | Liang et al. |
5642261 | June 24, 1997 | Bond et al. |
5648679 | July 15, 1997 | Chillara et al. |
5663593 | September 2, 1997 | Mostafazadeh et al. |
5668405 | September 16, 1997 | Yamashita |
5674785 | October 7, 1997 | Akram et al. |
5675180 | October 7, 1997 | Pedersen et al. |
5677566 | October 14, 1997 | King et al. |
5682061 | October 28, 1997 | Khandros et al. |
5689091 | November 18, 1997 | Hamzehdoost et al. |
5696033 | December 9, 1997 | Kinsman |
5714405 | February 3, 1998 | Tsubosaki et al. |
5723907 | March 3, 1998 | Akram |
5729432 | March 17, 1998 | Shim et al. |
5734198 | March 31, 1998 | Stave |
5739585 | April 14, 1998 | Akram et al. |
5739588 | April 14, 1998 | Ishida et al. |
5741622 | April 21, 1998 | Arima |
5744862 | April 28, 1998 | Ishii |
5767575 | June 16, 1998 | Lan et al. |
5770347 | June 23, 1998 | Saitoh et al. |
5780923 | July 14, 1998 | Courtenay |
5783866 | July 21, 1998 | Lee et al. |
5783870 | July 21, 1998 | Mostafazadeh et al. |
5789803 | August 4, 1998 | Kinsman |
5796586 | August 18, 1998 | Lee et al. |
5804874 | September 8, 1998 | An et al. |
5804880 | September 8, 1998 | Mathew |
5811879 | September 22, 1998 | Akram |
5814883 | September 29, 1998 | Sawai et al. |
5815372 | September 29, 1998 | Gallas |
5818698 | October 6, 1998 | Corisis |
5834945 | November 10, 1998 | Akram et al. |
5835988 | November 10, 1998 | Ishii |
5844315 | December 1, 1998 | Melton et al. |
5848467 | December 15, 1998 | Khandros et al. |
5852326 | December 22, 1998 | Khandros et al. |
5883426 | March 16, 1999 | Tokuno et al. |
5893726 | April 13, 1999 | Farnworth et al. |
5903049 | May 11, 1999 | Mori |
5915169 | June 22, 1999 | Heo |
5915977 | June 29, 1999 | Hembree et al. |
5920118 | July 6, 1999 | Kong |
5931685 | August 3, 1999 | Hembree et al. |
5933710 | August 3, 1999 | Chia et al. |
5950304 | September 14, 1999 | Khandros et al. |
5952611 | September 14, 1999 | Eng et al. |
5962921 | October 5, 1999 | Farnworth et al. |
5963430 | October 5, 1999 | Londa |
5990547 | November 23, 1999 | Sharma et al. |
5994166 | November 30, 1999 | Akram et al. |
6013946 | January 11, 2000 | Lee et al. |
6013948 | January 11, 2000 | Akram et al. |
6020629 | February 1, 2000 | Farnworth et al. |
6028365 | February 22, 2000 | Akram et al. |
6046072 | April 4, 2000 | Matsuura et al. |
6048755 | April 11, 2000 | Jiang et al. |
6057597 | May 2, 2000 | Farnworth et al. |
6072233 | June 6, 2000 | Corisis et al. |
6091140 | July 18, 2000 | Toh et al. |
6097085 | August 1, 2000 | Ikemizu et al. |
6097087 | August 1, 2000 | Farnworth et al. |
6107109 | August 22, 2000 | Akram et al. |
6133627 | October 17, 2000 | Khandros et al. |
6201304 | March 13, 2001 | Moden |
6235554 | May 22, 2001 | Akram et al. |
6262477 | July 17, 2001 | Mahulikar et al. |
6265766 | July 24, 2001 | Moden |
6268649 | July 31, 2001 | Corisis et al. |
6331939 | December 18, 2001 | Corisis et al. |
6372527 | April 16, 2002 | Khandros et al. |
6392306 | May 21, 2002 | Khandros et al. |
6433419 | August 13, 2002 | Khandros et al. |
6455928 | September 24, 2002 | Corisis et al. |
6465893 | October 15, 2002 | Khandros et al. |
6825569 | November 30, 2004 | Jiang et al. |
6861290 | March 1, 2005 | Moden |
6869827 | March 22, 2005 | Vaiyapuri |
20010030370 | October 18, 2001 | Khandros et al. |
20020000652 | January 3, 2002 | Goh |
20020155728 | October 24, 2002 | Khandros et al. |
20030168253 | September 11, 2003 | Khandros et al. |
20050087855 | April 28, 2005 | Khandros et al. |
60-194548 | October 1985 | JP |
4-30544 | February 1992 | JP |
4-107964 | April 1992 | JP |
07-283274 | October 1995 | JP |
- Anthony, T.R., “Forming electrical interconnections through semiconductor wafers,” J. Appl. Phys., vol. 52, No. 8, Aug. 1981, pp. 5340-5349.
- “Chip Scale Review,” vol. 1, No. 1, May 1997.
- Roget's II, The New Thesaurus, 3rd Edition, Houghton Mifflin Company, 1995, p. 213.
- Random House Webster's College Dictionary, Random House, New York, 1997, p. 297.
Type: Grant
Filed: May 18, 2006
Date of Patent: Jan 17, 2012
Assignee: Round Rock Research, LLC (Mt. Kisco, NY)
Inventors: David J. Corisis (Nampa, ID), Jerry M. Brooks (Palmer, AK), Walter L. Moden (Boise, ID)
Primary Examiner: Tan N Tran
Attorney: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
Application Number: 11/438,125
International Classification: H01L 21/00 (20060101);