Abstract: A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.

Abstract: A method for using a system to compute a solution to a partial differential equation (PDE) broadly comprises the steps of determining the true accuracy required (TAR) to solve the PDE, determining an architecture according to the TAR that performs a plurality of calculations to solve the PDE, determining a time allowed (TA) and a time required (TR) based on the architecture to solve the PDE, rejecting the PDE if the TR is less than or equal to the TA, configuring a plurality of programmable devices with the architecture, initiating the calculations, and ceasing the calculations when an accuracy criteria is met or when the TA expires. The system broadly comprises a plurality of programmable devices, a plurality of storage elements, a device bus, a plurality of printed circuit (PC) boards, and a board to board bus.

Abstract: Provided is a method and system for noise-driven recovery of a digital pulse stream. The method includes receiving initial parameters including the base characteristics of a pulse signal, the characteristics including the minimum pulse interval. An incoming analog signal is converted to a digital signal and sampled a predetermined number of times at intervals less than the minimum pulse interval to record a set of minimum signal values. The incoming signal is also sampled a predetermined number of times at intervals less than the minimum pulse interval to record a set of maximum signal values. At least the first greatest value from the set of maximum signal values is discarded. Each set is averaged to provide an average minimum value and an average maximum value. Based on these values at least one threshold value is then determined, and the digital pulse stream is identified based on the threshold values.

Abstract: Reconfigurable communications infrastructures may be implemented to interconnect ASIC devices (e.g., FPGAs) and other computing and input/output devices using high bandwidth interconnection mediums. The computing and input/output devices may be positioned in locations that are physically segregated from each other, and/or may be provided to project a reconfigurable network across a wide area. The reconfigurable communications infrastructures may be implemented to allow such computing and input/output devices to be used in different arrangements and applications, e.g., for use in any application where a large array of ASIC devices may be usefully employed such as supercomputing, etc.

Abstract: Provided is a programmable matrix element or “PME” (which may be part of an ASIC central processing unit) operable to manipulate a data set of real and complex numbers derived from an input signal. Specific operations may include: addition, subtraction, multiplication, accumulation, storage and scaling. Each PME includes a plurality of multi-stage signal processing modules, which may be two-staged modules. Each state, in turn, includes: at least one data manipulation module for manipulating the input signal; a crosspoint switch for facilitating the receipt and parallel distribution of an input signal/manipulated output signal; and a programmable control module operable to support data manipulation by controlling manipulation functions, storing data and routing signals. A given crosspoint switch may be programmed to interconnect data manipulation modules in “datapipe” fashion, which is to say via a specified number of parallel data pathways.

Abstract: Solderless and durable electrical contacts may be made by growing carbon nanotube (CNT) or nanowire forests in a solderless manner directly on the contact surfaces of integrated circuits, PCBs, IC packages, hybrid substrates, contact carriers, rotor components, stator components, etc. The electrical contacts and methods may be employed in a variety of leaded and leadless electronic packaging applications on PCBs, IC packages, and hybrid substrates including, but not limited to, ball grid array (BGA) packages, land grid array (LGA) and leadless chip carrier (LCC) packages, as well as for making interconnections in “flip-chip” configurations, “bare die” configurations, and interconnection of integrated circuit die in multi-layer and “3-D” stacking arrangements.

Abstract: One or more nodes of a network may be configured to provide substitute header information for insertion into a received data packet and then to retransmit the data packet with the modified header information to other network destinations. One or more other downstream nodes may be configured to do likewise, thus allowing a packet to proceed through a selected number of multiple destinations in the network without being shortened, and so that the number of control words required in each packet is reduced, in increasing data bandwidth for the network.

Abstract: Provided is a digital signal processing device, specifically a modular application specific integrated circuit (“ASIC”), having a programmable crosspoint switch for facilitating data transfer and processing within the circuit. A programmable matrix element is operable to perform advanced matrix operations (arithmetic operations) according to user provided commands. The crosspoint switch interconnects the programmable matrix element with various other processing or conditioning modules (i.e. down conversion, filter, pulse processing and demodulation modules) to ensure parallel processing at System Clock rates. The ASIC, which is reconfigurable at a top-level according to user requirements, facilitates design changes and bench testing.

Abstract: A system for identifying a person includes at least one biometric sensor for sensing a biometric characteristic of the person; at least one signal sensor for sensing a signal emitted from a device carried by the person; and a computing device for comparing the sensed biometric characteristic and the sensed signal to known characteristics of the person in an attempt to identify the person.

Abstract: Provided is a method and system for signal-driven recovery of a digital pulse stream. The method includes receiving initial parameters including the base characteristics of a pulse signal, the characteristics including the maximum pulse interval. An incoming analog signal is converted to a digital signal and sampled a predetermined number of times at intervals greater than the maximum pulse interval to record a set of minimum signal values and a set of maximum signal values. Each set is averaged to provide an average minimum value and an average maximum value. Based on these values at least one threshold value is then determined, and the digital pulse stream is identified based on the threshold values. The method is repetitive, continually re-determining the threshold values so as to adapt to changes in the incoming signal. A system for performing the method is also provided.

Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.

Abstract: Methods and systems for modeling concurrent behavior in a sequential programming environment using sequential-execution languages to describe and model multiple different processes which are running simultaneously.

Abstract: Systems and methods for providing a weighted overlap and add (WOLA) architecture and/or for providing polyphase WOLA FFT processing that may be employed, for example, for separation or channelization of closely-spaced frequencies of an input signal. A WOLA architecture that may be implemented as first-in-first-out (FIFO) cores in an FPGA or ASIC device. The FIFO cores may be pre-existing (e.g., provided as free FIFO cores in a commercial off the shelf (COTS) FPGA device) or may be custom-programmed into a custom ASIC device.

Abstract: Systems and methods are disclosed for forming reconfigurable neural networks with interconnected FPGAs each having a packet router. Neural network nodes are formed within the FPGAs and connections between nodes within an FPGA and connections to nodes external to the FPGA are made using packet routers that are configured within each FPGA. The FPGAs can be connected to each other using high-speed interconnects, such as high-speed serial digital interconnects. The FPGA arrays with packet routing allow for dynamic and reconfigurable neural networks to be formed thereby greatly improving the performance and intelligence of the neural network.

Abstract: Provided is a method and system for signal-driven recovery of a digital pulse stream. The method includes receiving initial parameters including the base characteristics of a pulse signal, the characteristics including the maximum pulse interval. An incoming analog signal is converted to a digital signal and sampled a predetermined number of times at intervals greater than the maximum pulse interval to record a set of minimum signal values and a set of maximum signal values. Each set is averaged to provide an average minimum value and an average maximum value. Based on these values at least one threshold value is then determined, and the digital pulse stream is identified based on the threshold values. The method is repetitive, continually re-determining the threshold values so as to adapt to changes in the incoming signal. A system for performing the method is also provided.

Abstract: Provided is a digital signal processing device, specifically a modular application specific integrated circuit (“ASIC”), having a programmable crosspoint switch for facilitating data transfer and processing within the circuit. A programmable matrix element is operable to perform advanced matrix operations (arithmetic operations) according to user provided commands. The crosspoint switch interconnects the programmable matrix element with various other processing or conditioning modules (i.e. down conversion, filter, pulse processing and demodulation modules) to ensure parallel processing at System Clock rates. The ASIC, which is reconfigurable at a top-level according to user requirements, facilitates design changes and bench testing.

Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.

Abstract: Application Specific Integrated Circuit (“ASIC”) devices, such as Field Programmable Gate Arrays (“FPGAs”), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (“MGT”) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (“RHA”) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Additionally, a communications infrastructure may be established across multiple circuit cards.

Abstract: Provided is a digital signal processing device, specifically a modular application specific integrated circuit (“ASIC”), having a programmable crosspoint switch for facilitating data transfer and processing within the circuit. A programmable matrix element is operable to perform advanced matrix operations (arithmetic operations) according to user provided commands. The crosspoint switch interconnects the programmable matrix element with various other processing or conditioning modules (i.e. down conversion, filter, pulse processing and demodulation modules) to ensure parallel processing at System Clock rates. The ASIC, which is reconfigurable at a top-level according to user requirements, facilitates design changes and bench testing.

Abstract: Systems and methods are disclosed for mapping large multiplexers defined in VHDL (Very high speed integrated circuit Hardware Description Language) code to circuitry within an FPGA (field programmable gate array) in order to reduce the time required to synthesize and decompose such VHDL structures into FPGAs. It was recognized that large multiplexers within a VHDL device description can cause significant delays in the synthesis and decomposition processes for forming FPGAs based upon the VHDL code. By splitting the multiplexer into a multiple level cascaded multiplexer structure, a significant reduction can be achieved in the time it takes to accomplish the synthesis and decomposition process for FPGAs. The determination of whether the multiplexer is large and should be split can be made by a user, by tool automation, or by both.