Abstract: Systems and methods are disclosed for forming reconfigurable neural networks with interconnected FPGAs each having a packet router. Neural network nodes are formed within the FPGAs and connections between nodes within an FPGA and connections to nodes external to the FGPA are made using packet routers that are configured within each FPGA. The FPGAs can be connected to each other using high-speed interconnects, such as high-speed serial digital interconnects. The FPGA arrays with packet routing allow for dynamic and reconfigurable neural networks to be formed thereby greatly improving the performance and intelligence of the neural network.

Abstract: One or more nodes of a network may be configured to provide substitute header information for insertion into a received data packet and then to retransmit the data packet with the modified header information to other network destinations. One or more other downstream nodes may be configured to do likewise, thus allowing a packet to proceed through a selected number of multiple destinations in the network without being shortened, and so that the number of control words required in each packet is reduced, in increasing data bandwidth for the network.