Patents by Inventor Jerry Yu
Jerry Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11995390Abstract: A circuit includes a first transistor, a second type-one transistor, a first type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor. Third type-one transistor has a second active-region and a gate conductively connected to each other. The fifth type-one transistor has a first active-region conductively connected with the gate of the third type-one transistor and has a second active-region configured to have a first supply voltage of a second power supply. The fifth type-one transistor is configured to be at a conducting state.Type: GrantFiled: December 9, 2022Date of Patent: May 28, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Jerry Chang Jui Kao, Pin-Dai Sue, Jiun-Jia Huang, Yu-Ti Su, Wei-Hsiang Ma
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Publication number: 20240160826Abstract: The routing of conductors in the conductor layers in an integrated circuit are routed using mixed-Manhattan-diagonal routing. Various techniques are disclosed for selecting a conductor scheme for the integrated circuit prior to fabrication of the integrated circuit. Techniques are also disclosed for determining the supply and/or the demand for the edges in the mixed-Manhattan-diagonal routing.Type: ApplicationFiled: November 17, 2023Publication date: May 16, 2024Inventors: Sheng-Hsiung Chen, Huang-Yu Chen, Chung-Hsing Wang, Jerry Chang Jui Kao
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Patent number: 11983479Abstract: A method of fabricating an integrated circuit includes placing a first set of conductive feature patterns on a first level, placing a second set of conductive feature patterns on a second level, placing a first set of via patterns between the second set of conductive feature patterns and the first set of conductive feature patterns, placing a third set of conductive feature patterns on a third level different from the first level and the second level, placing a second set of via patterns between the third set of conductive feature patterns and the second set of conductive feature patterns, and manufacturing the integrated circuit based on at least one of the above patterns of the integrated circuit.Type: GrantFiled: August 10, 2022Date of Patent: May 14, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung-Chan Yang, Ting-Wei Chiang, Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu, Li-Chun Tien, Meng-Hung Shen, Shang-Chih Hsieh, Chi-Yu Lu
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Patent number: 11979158Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.Type: GrantFiled: May 26, 2022Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Yu Lin, Yung-Chen Chien, Jia-Hong Gao, Jerry Chang Jui Kao, Hui-Zhong Zhuang
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Patent number: 11962193Abstract: Embodiments disclosed herein describe methods for improved permanent magnet motor rotor systems for submersible electric motors. The improved rotor system includes a single piece of material shaft with surface mounted permanent magnets. The single piece of material shaft minimizes the number of shaft bearings and locates the bearings outside of the stator windings.Type: GrantFiled: September 16, 2020Date of Patent: April 16, 2024Assignee: RLT Holdings, LLCInventors: Edward Curt, Kyle Meier, Jerry Yu, Samuel Rodriguez
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Publication number: 20240067746Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.Type: ApplicationFiled: February 28, 2023Publication date: February 29, 2024Inventors: Tong-Hsuan CHANG, Mei-Chun YANG, Liahng-Yirn LIU, Jerry TING, Shu-Yen CHANG, Yen-Ying CHEN, Yu-Yu LIN, Shu-Lun TANG
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Patent number: 11843047Abstract: In some embodiments, the present disclosure relates to an integrated transistor device, including a first barrier layer arranged over a substrate. Further, an undoped layer may be arranged over the first barrier layer and have a n-channel device region laterally next to a p-channel device region. The n-channel device region of the undoped layer has a topmost surface that is above a topmost surface of the p-channel device region of the undoped layer. The integrated transistor device may further comprise a second barrier layer over the n-channel device region of the undoped layer. A first gate electrode is arranged over the second barrier layer, and a second gate electrode is arranged over the p-channel device region of the undoped layer.Type: GrantFiled: May 24, 2022Date of Patent: December 12, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
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Publication number: 20230387281Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.Type: ApplicationFiled: August 3, 2023Publication date: November 30, 2023Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
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Patent number: 11824109Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.Type: GrantFiled: July 20, 2022Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
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Publication number: 20230369449Abstract: The transistor includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer.Type: ApplicationFiled: July 27, 2023Publication date: November 16, 2023Inventors: Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 11804538Abstract: A method of forming a high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.Type: GrantFiled: May 26, 2021Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Fu-Chih Yang, Chun Lin Tsai
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Patent number: 11791388Abstract: In some embodiments, the present disclosure relates to a transistor device. The transistor device that includes a source contact disposed over a substrate. The source contact has a first side and an opposing second side disposed between a first end and an opposing second end. A drain contact is disposed over the substrate and is separated from the source contact along a first direction. A gate structure is disposed over the substrate between the source contact and the drain contact. The gate structure extends along the first side of the source contact facing the drain contact and also wraps around the first end and the opposing second end of the source contact.Type: GrantFiled: April 30, 2020Date of Patent: October 17, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Aurelien Gauthier Brun, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Yun-Hsiang Wang
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Publication number: 20230299133Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate. A doped isolation region is disposed within the substrate and includes a horizontally extending segment and one or more vertically extending segments extending outward from the horizontally extending segment. The substrate includes a first sidewall and a second sidewall separated from the first sidewall a non-zero distance. The non-zero distance is directly over the one or more vertically extending segments.Type: ApplicationFiled: May 26, 2023Publication date: September 21, 2023Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
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Publication number: 20230261066Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of source contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate. The plurality of gate structures wrap around one or more of the plurality of source contacts in one or more closed loops. A drain contact is disposed over the substrate. The drain contact continuously wraps around one or more of the plurality of gate structures as a continuous structure. The plurality of gate structures are separated from the drain contact by a first distance and are separated from a source contact of the plurality of source contacts by a second distance. The second distance is different than the first distance.Type: ApplicationFiled: April 18, 2023Publication date: August 17, 2023Inventors: Aurelien Gauthier Brun, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Yun-Hsiang Wang
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Patent number: 11715792Abstract: Various embodiments of the present disclosure are directed toward an integrated chip including an undoped layer overlying a substrate. A first barrier layer overlies the undoped layer. A doped layer overlies the first barrier layer. Further, a second barrier layer overlies the first barrier layer, where the second barrier layer is laterally offset from a perimeter of the doped layer by a non-zero distance. The first and second barrier layers comprise a same III-V semiconductor material. A first atomic percentage of a first element within the first barrier layer is less than a second atomic percentage of the first element within the second barrier layer.Type: GrantFiled: May 12, 2020Date of Patent: August 1, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yun-Hsiang Wang, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Chia-Ling Yeh, Ching Yu Chen
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Patent number: 11705486Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first III-V semiconductor material over a substrate and a second III-V semiconductor material over the first III-V semiconductor material. The second III-V semiconductor material is a different material than the first III-V semiconductor material. A doped region has a horizontally extending segment and one or more vertically extending segments protruding vertically outward from the horizontally extending segment. The horizontally extending segment is arranged below the first III-V semiconductor material.Type: GrantFiled: October 27, 2020Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Man-Ho Kwan
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Patent number: 11664431Abstract: The present disclosure relates to a transistor device. The transistor device includes a plurality of first source/drain contacts disposed over a substrate. A plurality of gate structures are disposed over the substrate between the plurality of first source/drain contacts. The plurality of gate structures wrap around the plurality of first source/drain contacts in a plurality of closed loops. A second source/drain contact is disposed over the substrate between the plurality of gate structures. The second source/drain contact continuously wraps around the plurality of gate structures as a continuous structure.Type: GrantFiled: January 8, 2021Date of Patent: May 30, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Aurelien Gauthier Brun, Chun Lin Tsai, Jiun-Lei Jerry Yu, Po-Chih Chen, Yun-Hsiang Wang
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Publication number: 20230123907Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.Type: ApplicationFiled: December 19, 2022Publication date: April 20, 2023Inventors: YAO-CHUNG CHANG, PO-CHIH CHEN, JIUN-LEI JERRY YU, CHUN LIN TSAI
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Patent number: 11532740Abstract: A semiconductor structure includes: a channel layer; an active layer over the channel layer, wherein the active layer is configured to form a two-dimensional electron gas (2DEG) to be formed in the channel layer along an interface between the channel layer and the active layer; a gate electrode over a top surface of the active layer; and a source/drain electrode over the top surface of the active layer; wherein the active layer includes a first layer and a second layer sequentially disposed therein from the top surface to a bottom surface of the active layer, and the first layer possesses a higher aluminum (Al) atom concentration compared to the second layer. An HEMT structure and an associated method are also disclosed.Type: GrantFiled: March 19, 2021Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yao-Chung Chang, Po-Chih Chen, Jiun-Lei Jerry Yu, Chun Lin Tsai
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Patent number: 11522077Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.Type: GrantFiled: May 27, 2020Date of Patent: December 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang