Patents by Inventor Jesse Daniels

Jesse Daniels has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8898233
    Abstract: A matchmaking system is provided herein to facilitate the development of relationships in a virtual social environment. The amount of development (positive or negative) is measured through the detection and analysis of the villager's actions and activity in the virtual social environment. By performing actions including participating in events, activities, sharing an opinion, and giving gifts to other villagers or NPCs present in the environment, a villager creates relationships between herself and other villagers (regardless if owned by the same or different user) or NPCs which then contributes to the development of her own “life” in the virtual social environment. Through this system, villagers are able to meet again based on multiple factors to further develop life-like relationships.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: November 25, 2014
    Assignee: Ganz
    Inventors: Joseph Benjamin Ganetakos, Jesse Daniel Scoble, John Alexander Larsen, Karl Joseph Borst
  • Publication number: 20140249143
    Abstract: Provided are certain compounds and pharmaceutically acceptable salts thereof, their pharmaceutical compositions, their methods of preparation, and their use for treating viral infections.
    Type: Application
    Filed: October 19, 2012
    Publication date: September 4, 2014
    Applicant: GlaxoSmithKline LLC
    Inventors: Anna Lindsey Banka, Janos Botyanszki, Eric Gregory Burroughs, John George Catalano, Wendy Huang Chern, Hamilton D. Dickson, Margaret J. Gartland, Robert Hamatake, Hans Hofland, Jesse Daniel Keicher, Christopher Brooks Moore, John Bradford Shotwell, Matthew David Tallant, Jean-Philippe Therrien, Shihyun You
  • Patent number: 8726555
    Abstract: A magazine safety assembly configured for use in a firearm includes a pivot point assembly. A lever assembly, including a first portion and a second portion, is configured to pivot about the pivot point assembly from an engaged position to a disengaged position. When positioned in the engaged position, the first portion of the lever assembly releasably engages a trigger assembly of the firearm. When positioned in the disengaged position, the second portion of the lever assembly releasably engages an ammunition magazine assembly positioned within a magazine well of the firearm. A spring assembly is configured to bias the lever assembly into the engaged position when the ammunition magazine assembly is not positioned within the magazine well the firearm.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: May 20, 2014
    Assignee: Sig Sauer, Inc.
    Inventor: Jesse Daniel Carr
  • Patent number: 8719730
    Abstract: A user interface for a virtual world includes a circular area forming a display for an item in the virtual world, and controls surrounding only a portion of the display for controlling that item.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: May 6, 2014
    Assignee: Ganz
    Inventors: Joseph Benjamin Ganetakos, Frank James Caron, Jesse Daniel Scoble, Gord Scott McLeod, John Alexander Larsen, Felix Leung, Karl Joseph Borst
  • Patent number: 8581727
    Abstract: Apparatuses, methods, and systems for alerting a golfer when one or more golf clubs are misplaced from a group of golf clubs. A peripheral unit is associated with and affixed to each of a number of golf clubs, and transmits signals that are detected and collectively processed by a base unit to determine the status of those clubs. A club may be designated as misplaced based on the sequence and timing of status events, upon which an alarm is activated to alert the golfer.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: November 12, 2013
    Inventors: Jesse Daniel Koenig, Matthew Charles Smiley
  • Publication number: 20130239303
    Abstract: A tightening system can be used with a helmet or other wearable article. The tightening system can have a forehead strap that is space apart from a yoke, which can be configured to engage a back side of a wearer's head. A lace can extend between the forehead strap and the yoke and a tightening mechanism can be configured to adjust tension on the lace. One or more intermediate tenders can engage the lace in the gap between the forehead strap and the yoke so that the lace path between the forehead strap and the yoke is non-linear. The yoke can have a height adjustment mechanism. The tightening mechanism can be configured to provide a clicking sound during rotation in both the tightening direction and the loosening direction. The tightening mechanism can include a rotation limiter to prevent over-tightening and/or over-loosening of the tightening mechanism.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 19, 2013
    Applicant: BOA TECHNOLOGY, INC.
    Inventors: JESSE DANIEL COTTERMAN, CHRISTOPHER HOYT CONVERSE
  • Publication number: 20120291325
    Abstract: A magazine safety assembly configured for use in a firearm includes a pivot point assembly. A lever assembly, including a first portion and a second portion, is configured to pivot about the pivot point assembly from an engaged position to a disengaged position. When positioned in the engaged position, the first portion of the lever assembly releasably engages a trigger assembly of the firearm. When positioned in the disengaged position, the second portion of the lever assembly releasably engages an ammunition magazine assembly positioned within a magazine well of the firearm. A spring assembly is configured to bias the lever assembly into the engaged position when the ammunition magazine assembly is not positioned within the magazine well the firearm.
    Type: Application
    Filed: April 23, 2012
    Publication date: November 22, 2012
    Inventor: JESSE DANIEL CARR
  • Publication number: 20110264741
    Abstract: A matchmaking system is provided herein to facilitate the development of relationships in a virtual social environment. The amount of development (positive or negative) is measured through the detection and analysis of the villager's actions and activity in the virtual social environment. By performing actions including participating in events, activities, sharing an opinion, and giving gifts to other villagers or NPCs present in the environment, a villager creates relationships between herself and other villagers (regardless if owned by the same or different user) or NPCs which then contributes to the development of her own “life” in the virtual social environment. Through this system, villagers are able to meet again based on multiple factors to further develop life-like relationships.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 27, 2011
    Applicant: GANZ
    Inventors: Joseph Benjamin Ganetakos, Jesse Daniel Scoble, John Alexander Larsen, Karl Joseph Borst
  • Publication number: 20110265044
    Abstract: A user interface for a virtual world controls and allows registering new characters and also registering achievement when the user has carried out a number of different items.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 27, 2011
    Applicant: GANZ
    Inventors: Joseph Benjamin Ganetakos, Frank James Caron, Jesse Daniel Scoble, Gord Scott McLeod, John Alexander Larsen, Felix Leung, Karl Joseph Borst
  • Publication number: 20110265041
    Abstract: A user interface for a virtual world includes a circular area forming a display for an item in the virtual world, and controls surrounding only a portion of the display for controlling that item.
    Type: Application
    Filed: April 21, 2011
    Publication date: October 27, 2011
    Applicant: GANZ
    Inventors: Joseph Benjamin Ganetakos, Frank James Caron, Jesse Daniel Scoble, Gord Scott McLeod, John Alexander Larsen, Felix Leung, Karl Joseph Borst
  • Patent number: 7925950
    Abstract: A method and circuit for implementing substantially perfect array access time tracking with Logic Built In Self Test (LBIST) diagnostics of dynamic memory array and random logic, and a design structure on which the subject circuit resides are provided. The dynamic memory array is initialized to a state for the longest read time for each bit and the dynamic memory array is forced into a read only mode. During LBIST diagnostics with the array in the read only mode, the array outputs are combined with the data inputs to provide random switching data on the array outputs to the random logic.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Todd Alan Christensen, Peter Thomas Freiburger, Jesse Daniel Smith
  • Patent number: 7911827
    Abstract: An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.
    Type: Grant
    Filed: January 27, 2009
    Date of Patent: March 22, 2011
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Publication number: 20110044943
    Abstract: Disclosed are compounds of Formula (I), pharmaceutically acceptable salts and solvates thereof, compositions thereof, and methods for their preparation and uses for treating viral infections mediated at least in part by a virus in the Flaviviridae family of viruses.
    Type: Application
    Filed: July 11, 2008
    Publication date: February 24, 2011
    Inventors: Martin Robert Leivers, Jesse Daniel Keicher, Franz Ulrich Schmitz, Roopa Rai, Ryan Lauchli, Sebastian Reinhard Johannes Liehr, Stephanie Anna Chan, Tony Loc Ton
  • Patent number: 7844869
    Abstract: A method and circuit implement testing of a circuit path including a memory array and logic including Logic Built in Self Test (LBIST) diagnostics, and a design structure on which the subject circuit resides are provided. Testing of the circuit path includes initializing the memory array in the circuit path with an initialization pattern, switching to Logic Built in Self Test (LBIST) mode and providing a read only mode for the memory array, and running Logic Built in Self Test (LBIST) testing of the circuit path.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: November 30, 2010
    Assignee: International Business Machines Corporation
    Inventors: Louis Bernard Bushard, Todd Alan Christensen, Jesse Daniel Smith
  • Publication number: 20100218055
    Abstract: A method and circuit for implementing substantially perfect array access time tracking with Logic Built In Self Test (LBIST) diagnostics of dynamic memory array and random logic, and a design structure on which the subject circuit resides are provided. The dynamic memory array is initialized to a state for the longest read time for each bit and the dynamic memory array is forced into a read only mode. During LBIST diagnostics with the array in the read only mode, the array outputs are combined with the data inputs to provide random switching data on the array outputs to the random logic.
    Type: Application
    Filed: February 26, 2009
    Publication date: August 26, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Todd Alan Christensen, Peter Thomas Freiburger, Jesse Daniel Smith
  • Publication number: 20100188886
    Abstract: An array built in self test (ABIST) method and circuit for implementing enhanced static random access memory (SRAM) stability and enhanced chip yield using configurable wordline voltage levels, and a design structure on which the subject circuit resides are provided. A wordline is connected to a SRAM memory cell. A plurality of wordline voltage pulldown devices is connected to the wordline. A respective wordline voltage control input signal is applied to each of the plurality of wordline voltage pulldown devices to selectively adjust the voltage level of the wordline.
    Type: Application
    Filed: January 27, 2009
    Publication date: July 29, 2010
    Applicant: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Patent number: 7737757
    Abstract: Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: June 15, 2010
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Patent number: 7724585
    Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.
    Type: Grant
    Filed: August 20, 2008
    Date of Patent: May 25, 2010
    Assignee: International Business Machines Corporation
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Publication number: 20100046277
    Abstract: A method and circuit for implementing domino static random access memory (SRAM) local evaluation with enhanced SRAM cell stability, and a design structure on which the subject circuit resides are provided. A SRAM local evaluation circuit enabling a read and write operations of an associated SRAM cell group includes true and complement bitlines, a single write data propagation input, a precharge signal, and a precharge write signal. A passgate device is connected between the complement bitline and the write data propagation input. A transistor stack is connected in series with the precharge device between the true bitline and ground. The precharge write signal disables the passgate device connected between the complement bitline and the write data propagation input during a read operation. During write operations, the precharge write signal enables the passgate device connected between the complement bitline and the write data propagation input and activates the transistor stack.
    Type: Application
    Filed: August 20, 2008
    Publication date: February 25, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith
  • Publication number: 20100019824
    Abstract: Low power level shifter latch circuits with gated feedback for high speed integrated circuits, and a design structure on which the subject circuit resides are provided. A latch input stage operating in a domain of a first voltage supply receives a data input responsive to being enabled by predefined clock signals. A latch storage element coupled to the latch input stage includes a latch output stage operating in a domain of a second voltage supply provides a data output having a voltage level corresponding to the second voltage supply. The latch storage element includes a level shifting device providing level shifting from the first supply level to the second voltage supply level. The latch storage element includes feedback gate devices receiving the predefined clock signals to gate feedback to the latch input stage when data is being written to the latch input stage.
    Type: Application
    Filed: July 23, 2008
    Publication date: January 28, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Derick Gardner Behrends, Travis Reynold Hebig, Daniel Mark Nelson, Jesse Daniel Smith