Abstract: A method of configuring an integrated circuit includes developing a circuit simulation model of a circuit having an output port to be configured in the integrated circuit. A number of simultaneously switched outputs (SSOs) are defined according to the circuit simulation model, and a propagation delay at the output port is characterized according to the number of SSOs. The circuit simulation model is back-annotated from the output port to add the propagation delay in a signal path of the output port to produce a second circuit simulation model. A configuration bitstream is generated according to the second circuit simulation model and the integrated circuit is configured according to the bitstream.

Abstract: Programmable logic devices (PLDs), programmable logic arrays (PLAs), complex programmable logic devices (CPLDs), and field programmable gate arrays (FPGAs), (collectively referred to as “PLDs”) can include circuitry for performing automatic erasing or “zeroization” of security information including data and programming. Such circuitry detects the occurrence of a possible security event, selects and/or forms one or more appropriate erase commands, and causes the command(s) to be executed against PLD memory. The circuitry prevents security information from being compromised under certain situations.

Abstract: An integrated circuit having secure configuration includes configuration memory, programmable logic resources coupled to the configuration memory, programmable interconnection resources coupled to the configuration memory and programmable logic resources, and a configuration controller circuit coupled to the configuration memory. The configuration controller circuit is configured to read values from a configuration memory address of a portion of the configuration memory in response to a configuration memory address contained in input configuration data, and to decrypt the input configuration data using the values as a decryption key. The configuration controller is further configured to program the configuration memory of the integrated circuit with the decrypted input configuration data.

Abstract: A method of implementing output ports of a programmable integrated circuit is disclosed. The method comprises coupling control signals to predetermined output ports of the integrated circuit; setting, by the control signals, initial output values of the predetermined output ports during programming of the programmable integrated circuit; and enabling normal operation of the predetermined output ports after the programming of the programmable integrated circuit. An integrated circuit having programmable output ports is also disclosed.

Abstract: A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed.

Abstract: Approaches for secure configuration of a programmable logic integrated circuit (IC). In one approach, a method includes programming configuration memory of the programmable logic IC with a first configuration bitstream. At least a portion of a second configuration bitstream is encrypted using values stored in a portion of the configuration memory as a key. The second configuration bitstream is input to the programmable logic IC, and the encrypted portion of the second configuration bitstream is decrypted using the values stored in the portion of the configuration memory. The configuration memory is then programmed with each decrypted portion of the second bitstream.

Abstract: An arrangement and method of reducing power in bidirectional I/O ports includes driving an input signal from an I/O port by asserting a high impedance (Hi-Z) signal to an output drive, driving an output signal from the I/O port by refraining from asserting a Hi-Z signal to an output driver, and feeding back the output signal to an input driver when driving the output signal. The method can float the I/O port when the Hi-Z signal is asserted on the output driver or drive the I/O port as an input when the Hi-Z signal is asserted on the output driver. The method can refrain from floating a signal back into the I/O port when driving a signal out by driving a constant logical zero back into the I/O port or driving a constant logical one back or by maintaining a last value driven.

Abstract: A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal adaptation occurs through duty cycle correction (DCC) to substantially achieve a 50% duty cycle. In an alternate embodiment, clock signal adaptation occurs through a multiplication operation that is applied to the clock signal to be adapted, whereby the multiplication operation is parameterizable to allow odd/even multiplication. In an alternate embodiment, clock signal adaptation occurs through a phase-shift operation that is applied to the clock signal to be adapted, whereby the phase-shift operation is parameterizable to allow all possible fractions and percentages of phase shifts.

Abstract: A method and apparatus to implement clock signal adaptation is provided to characterize an input clock signal that is to be adapted and in response, generate adaptation updates at each subsequent clock cycle of the input clock signal. In a first embodiment, clock signal adaptation occurs through duty cycle correction (DCC) to substantially achieve a 50% duty cycle. In an alternate embodiment, clock signal adaptation occurs through a multiplication operation that is applied to the clock signal to be adapted, whereby the multiplication operation is parameterizable to allow odd/even multiplication. In an alternate embodiment, clock signal adaptation occurs through a phase-shift operation that is applied to the clock signal to be adapted, whereby the phase-shift operation is parameterizable to allow all possible fractions and percentages of phase shifts.

Abstract: A method of minimizing power consumption in an integrated device is disclosed. The method comprises providing a plurality of circuit blocks having circuits for performing logic functions, wherein each circuit block consumes power in a static state; coupling one of a plurality of operating voltages to each circuit block of the plurality of circuit blocks; enabling a reduction of power consumed by a first set of circuit blocks by way of a first power reduction signal; and enabling a reduction of power consumed by a second set of circuit blocks by way of a second power reduction signal. A circuit for minimizing power consumption in a device is also disclosed.

Abstract: Method for power estimation for mobile devices for content downloading is described. More particularly, likelihood of download success is determined responsive to user selection of downloadable content after establishment of a connection between a mobile device and a network. Capabilities of the mobile device are obtained. The power level of the mobile device is obtained. At least one download data rate is determined. A likelihood of success for downloading the downloadable content selected responsive to the at least one download data rate, the power level of the mobile device, and at least one capability from the capabilities of the mobile device is determined.

Abstract: Method and apparatus for providing secure programmable logic devices is described. One aspect of the invention relates to securing a programmable logic device having instruction register logic coupled to control logic via an instruction bus. A non-volatile memory is provided for storing at least one security bit for at least one instruction associated with the programmable logic device. Gating logic is provided in communication with the non-volatile memory and at least a portion of the instruction bus. The gating logic is configured to selectively gate decoded instructions transmitted from the instruction register logic towards the control logic based on state of the at least one security bit.

Abstract: An integrated circuit device such as a PLD is divided into a plurality of logic blocks, each including one or more resources of the device. The device includes a plurality of switch elements and a number of signal isolation circuits. The switch elements selectively disable corresponding logic blocks to reduce power consumption, and the signal isolation circuits selectively isolates corresponding logic blocks to prevent the transmission of invalid data from disabled logic blocks to enabled logic blocks.

Abstract: Methods and structures for design security in configurable devices are described. In some embodiments, a configurable device may be placed in an unsecured mode allowing for access to configuration data and other diagnostic functions during development and production phases. Once the device is finalized, it may be placed in a secure mode that disables a configuration path and enables a bypass path, thereby securing the configuration data. In some embodiments, the configurable device may be a programmable logic device, such as a complex programmable logic device.

Abstract: A programmable power-failure-detection circuit in an integrated circuit is provided that permits programmable selection of operating modes that either monitor a power supply of the integrated circuit or provide reduced power consumption from the power supply by disabling the monitoring of the power supply. The programmable power-failure-detection circuit includes at least one configurable memory cell, a monitor circuit, and a switch circuit disposed on the integrated circuit. The monitor circuit is adapted to monitor the power supply of the integrated circuit and generate a power failure signal in response to the power supply failing to comply with a prescribed operating specification. The switch circuit is coupled to the at least one configurable memory cell and the monitor circuit. The switch circuit is adapted to disable the monitor circuit in response to the at least one configurable memory cell.

Abstract: Methods of reducing the amount of logic in a digital circuit without affecting the functionality of the circuit. A circuit description and one or more test patterns are supplied to a fault simulator. The fault simulator runs the test patterns on the circuit, and identifies any nodes that did not transition in either direction (“non-transitioning nodes”). If the test patterns provide full coverage of the desired functionality for the circuit, each of the non-transitioning nodes is unnecessary to the logical functionality of the circuit in the target application. Therefore, the logic driving the non-transitioning nodes is removed from the circuit. The modified circuit can then be re-simulated, if desired, to verify that the relevant functionality of the circuit has not changed.

Abstract: A performance monitor is realized from programmable logic on the same integrated circuit as a processor. A user may use a programming and analysis tool to select a performance monitor soft core and to program it into the integrated circuit. The performance monitor is used to debug and/or monitor operation of the processor. After the debugging and/or performance monitoring, the portion of the programmable logic used to realize the performance monitor can be reconfigured and used to realize another portion of the user-specific circuit. Because the portion of the integrated circuit used to realize the performance monitor can be later used in the user-specific design, the cost of having to provide a no-longer-desired performance monitor in each integrated circuit used in the user's design is avoided. Because the performance monitor is realized from programmable logic, the performance monitor is more flexible than a conventional hardwired configurable performance monitor.

Abstract: An integrated circuit (IC) includes volatile memories, at least one non-volatile memory, at least one control circuit, and a configurable logic array. Each volatile memory has an associated interface including a respective first input and a respective second input. The control circuit is coupled to the volatile memories and the non-volatile memory. The control circuit stores respective contents from each volatile memory in the non-volatile memory responsive to the respective first input, and loads the respective contents into each volatile memory from the non-volatile memory responsive to the respective second input. The configurable logic array is coupled to the volatile memories and is configurable to control each first input and each second input.

Abstract: A programmable logic device (PLD) includes a plurality of segments, a plurality of segment-enable registers, and a configuration controller. Each segment-enable register is arranged to be set to a first value in response to resetting of the PLD. Each segment includes configurable logic that is associated with a respective segment-enable register. In addition, each segment is arranged to enable the configurable logic in response to a second value for the associated segment-enable register. The configuration controller is adapted to program the respective configurable logic in each segment to perform a respective function based on configuration data and to set each segment-enable register to the second value.

Abstract: A programmable logic device includes a function block to generate a power control signal that is distributed on a rail to selectively power down various components on the device. The rail is coupled to an observation pin to allow for external observation of the power control signal. The power control signal is also provided as a feed forward signal to an input signal blocking circuit, which selectively enables or disables the device input pins in response to the feed forward signal. The feed forward signal is not accessible from the observation pin, and therefore cannot be externally altered from the observation pin.