Abstract: A power control output circuit for a PLD that allows the PLD to selectively operate in either a low current (“normal”) output mode, or a high current power control mode. In one embodiment, the power control output circuit is incorporated into a special Input/Output Blocks (PC-IOB) of the PLD. When no power control function is needed, a high current output portion of the power control output circuit is deactivated by storing an associated data value a power control configuration memory cell of the PLD, and an output driver of the PC-IOB generates low current output signals on a device I/O terminal. To perform power control functions, a portion of the PLD's programmable logic circuitry is configured to generate a power control data signal, and the high current output portion of the power control output circuit is enabled by storing a corresponding data value in the power control configuration memory cell.

Abstract: The Internet is used to test an integrated circuit chip that is provided with boundary scan circuitry and plugged into a circuit board at a customer's location. A host computer at the manufacturer's location runs a web page server having the ability to remotely test a customer's chip. The process is initiated by the customer connecting the circuit board to his own computer and logging onto the web site. The customer transmits customer identification and other data to the web server, which then transmits a downloader program and a JAVA program script to the customer's computer. The customer's computer then uses the downloader program to transmit high and low level device data describing the functionality of the chip to the host computer, which then generates and transmits a set of suitable test vectors to the customer's computer.

Abstract: A programmable logic device including an adjustable length delay line formed by selectively connecting product-term elements in series. Switching circuits connected to the output terminals of each product-term element (e.g., logic AND gates) that allow the product terms to be routed either to the input terminals of a sum-of-products element (e.g., a logic OR gate), or to the input terminal of an adjacent product-term element. The length (i.e., actual signal delay) of the delay line is determined by the number of product-term elements that are connected in series. The output signal from the last product-term element in the series is transmitted through the sum-of-products element. Accordingly, the length of the delay line can be incrementally adjusted by programming the switches to add or subtract product-term elements from the delay line.

Abstract: A system including a programmable logic device (PLD) mounted on a populated printed circuit board, and a configuration processor. The PLD includes a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer. Each output buffer is coupled to an associated adjustable slew rate control circuit and to an adjustable delay line of the PLD. The configuration processor controls each of the slew rate control circuits to provide a first slew rate. The configuration processor also controls the output buffers to be coupled to the adjustable delay line. The configuration processor then controls the adjustable delay line to generate a first test pulse, which is applied to each of the output buffers. Depending on the impedances of the printed circuit board, the first test pulse transmitted from a particular output buffer may be reflected. Reflected test pulses return to the associated input buffers and are recorded.

Abstract: A method of minimizing power use in programmable logic devices (PLD) using programmable connections and scrap logic to create a versatile power management scheme. Individual product terms in a PLD can be powered off, thereby saving power, without incurring the power-up and settling time delays seen in the prior art. Power management is not restricted to any one function block, nor must the entire device be powered down, unless so programmed. All conventional logic functionality present in the PLD is available to the power management elements, allowing, in one embodiment, a standard function block to be programmed to operate as the control function block. This logic functionality includes, but is not limited to, internal feedback, combinatorial functions, and register functions. Because scrap logic resources left over from user programming and small programmable connections are used, minimal additional chip surface area is needed.

Abstract: A method of operating a pin of an in-system programmable logic device (ISPLD) which includes the steps of (1) applying a predetermined voltage to the pin when the ISPLD is in a set-up mode, and (2) maintaining the last voltage applied to the pin when the ISPLD is in a normal operating mode. The ISPLD is in the set-up mode when the logic of the ISPLD has not yet been configured, or is being configured. The ISPLD is in the normal operating mode after the logic of the ISPLD has been configured. A particular ISPLD includes a pin and a logic gate having a first input terminal coupled to the pin, a second input terminal coupled to receive a control signal, and an output terminal coupled to the pin. When the ISPLD is in the set-up mode, the control signal causes the logic gate to apply a predetermined voltage to the pin. When the ISPLD is in the normal operating mode, the control signal causes the logic gate to maintain the last applied voltage on the pin.

Abstract: A method for selecting the state assignments of a complex programmable logic device (CPLD) to minimize power consumption. Within the CPLD, a plurality of macrocells are selected to store a corresponding plurality of state variables, wherein the number of macrocells is selected to be equal to the number of states. For each of the states, one of the macrocells is assigned to store a state variable having a first logic state, and the remaining macrocells are assigned to store state variables having a second logic state. The macrocells storing state variables having the second logic state exhibit a lower power consumption than the macrocell storing the state variable having the first logic state. In addition, each of the macrocells includes a plurality of wired logic gates, each being in a high-current state or a low-current state. The number of wired logic gates in the low-current state is maximized in the macrocells assigned to store the state variables having the second logic state.

Abstract: A system including a programmable logic device (PLD) mounted on a populated printed circuit board, and a configuration processor. The PLD includes a plurality of input/output blocks (IOBs), each having an input buffer and an output buffer. Each output buffer is coupled to an associated adjustable slew rate control circuit and to an adjustable delay line of the PLD. The configuration processor controls each of the slew rate control circuits to provide a first slew rate. The configuration processor also controls the output buffers to be coupled to the adjustable delay line. The configuration processor then controls the adjustable delay line to generate a first test pulse, which is applied to each of the output buffers. Depending on the impedances of the printed circuit board, the first test pulse transmitted from a particular output buffer may be reflected. Reflected test pulses return to the associated input buffers and are recorded.

Abstract: In a programmable logic device having a plurality of external pins each of which may be driven by an output drive structure controlled by a programmable logic block, a logic device such as an OR gate or a programmable pull-up or pull-down switch is inserted between the input terminal of the output drive structure and the programmable logic block or other internal logic block which controls the output driver. This inserted structure allows the macrocell to be used for internal logic while the output drive structure is used to stabilize power or ground voltage.

Abstract: A macrocell for flexibly routing product terms from an AND array to output terminals of a programmable logic device. The macrocell allows a variable number of product terms to be retained by the macrocell, and a variable number of product terms to be exported to a second macrocell. The direction in which the product terms are exported can be controlled. The macrocell further allows a variable number of product terms to be received from a third macrocell and routed either to the output terminal of the first macrocell or to the second macrocell in combination with those product terms exported from the first macrocell. Methods for routing product terms using macrocells within a programmable logic device are also provided.

Abstract: An erasable programmable logic device (EPLD) includes function blocks connected by a universal interconnect matrix (UIM). The UIM includes both a cross-point circuit and a multiplexer-based (MUX-based) circuit. The cross-point circuit includes intersecting first and second conductors programmably connected by memory cells having control gates connected to the first conductors, drains connected to the second conductors, and sources connected to ground. The MUX-based circuit includes third and fourth conductors programmably connected by pass-gates having first terminals connected to the third conductors, second terminals connected to the fourth conductors, and gates connected to memory cells. The UIM further includes multiple-input multiplexers having first input lines connected to the cross-point circuit, second input lines connected to the MUX-based circuit, and output lines connected to the input lines of the function blocks.