Patents by Inventor Jessica S. Kachian

Jessica S. Kachian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210167216
    Abstract: Deep gate-all-around semiconductor devices having germanium or group 111-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10950733
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: March 16, 2021
    Assignee: Google LLC
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10553425
    Abstract: Embodiments described herein provide a self-limiting and saturating Si—Ox bilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO2, but instead produce a saturated Si—Ox film with —OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: February 4, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jessica S. Kachian, Naomi Yoshida, Mei Chang, Mary Edmonds, Andrew C. Kummel, Sang Wook Park, Hyunwoong Kim
  • Publication number: 20190326114
    Abstract: Methods for treating a substrate including: contacting a substrate having a top surface with a first self-assembled monolayer (SAM) precursor or a first small-molecule monolayer (SMM) precursor, a co-reactant, and a second SAM precursor or a second SMM precursor to form a first layer on the top surface. Selective deposition methods are also disclosed.
    Type: Application
    Filed: April 11, 2019
    Publication date: October 24, 2019
    Inventors: JESSICA S. KACHIAN, JUKKA TANSKANEN, WENYU ZHANG, MICHAEL S. JACKSON, CHANG KE, LIQI WU
  • Patent number: 10418487
    Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, the device includes a substrate having a top surface with a first lattice constant. Embedded epi source and drain regions are formed on the top surface of the substrate. The embedded epi source and drain regions have a second lattice constant that is different from the first lattice constant. A channel nanowire having a third lattice is formed between and are coupled to the embedded epi source and drain regions. In an embodiment, the second lattice constant and the third lattice constant are different from the first lattice constant. A gate dielectric layer is formed on and all-around the channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Ravi Pillarisetty, Van H. Le, Jack T. Kavalieros, Robert S. Chau, Jessica S. Kachian
  • Patent number: 10373824
    Abstract: Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300° C. and 500° C. A layered composition includes a first layer selected from the group consisting of InxGa1?xAs, InxGa1?xSb, InxGa1?xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: August 6, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Andrew C. Kummel, Mary Edmonds, Mei Chang, Jessica S. Kachian
  • Publication number: 20190148131
    Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.
    Type: Application
    Filed: January 15, 2019
    Publication date: May 16, 2019
    Inventors: Abhishek DUBE, Schubert S. CHU, Jessica S. KACHIAN, David THOMPSON, Jeffrey ANTHIS
  • Patent number: 10199215
    Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 5, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Schubert S. Chu, Jessica S. Kachian, David Thompson, Jeffrey Anthis
  • Publication number: 20180301563
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Application
    Filed: June 18, 2018
    Publication date: October 18, 2018
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10026845
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee
  • Patent number: 10008565
    Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Van H. Le, Ravi Pillarisetty, Jessica S. Kachian, Marc C. French, Aaron A. Budrevich
  • Patent number: 9896326
    Abstract: A method of reducing line bending and surface roughness of a substrate with pillars includes forming a treated surface by treating a pillar-containing substrate with a radical. The radical may be silicon-based, nitrogen-based or oxygen-based. The method may include forming a dielectric film over the treated surface by reacting an organosilicon precursor and an oxygen precursor. The method may include curing the dielectric film at a temperature of about 150° C. or less. A method of reducing line bending and surface roughness of a substrate with pillars includes forming a dielectric film over a pillar-containing substrate by reacting an organosilicon precursor, an oxygen precursor, and a radical precursor. The method may include curing the dielectric film at a temperature of about 150° C. or less. The radical precursor may be selected from the group consisting of nitrogen-based radical precursor, oxygen-based radical precursor, and silicon-based radical precursor.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: February 20, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Jingmei Liang, Kiran V. Thadani, Jessica S. Kachian, Nagarajan Rajagopalan
  • Publication number: 20180033610
    Abstract: Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300° C. and 500° C. A layered composition includes a first layer selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.
    Type: Application
    Filed: October 6, 2017
    Publication date: February 1, 2018
    Inventors: Andrew C. KUMMEL, Mary EDMONDS, Mei CHANG, Jessica S. KACHIAN
  • Publication number: 20180019116
    Abstract: Embodiments described herein provide a self-limiting and saturating Si—Ox bilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO2, but instead produce a saturated Si—Ox film with —OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials.
    Type: Application
    Filed: September 25, 2017
    Publication date: January 18, 2018
    Inventors: Jessica S. KACHIAN, Naomi YOSHIDA, Mei CHANG, Mary EDMONDS, Andrew C. KUMMEL, Sang Wook PARK, Hyunwoong KIM
  • Publication number: 20170352531
    Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.
    Type: Application
    Filed: August 23, 2017
    Publication date: December 7, 2017
    Inventors: Abhishek DUBE, Schubert S. CHU, Jessica S. KACHIAN, David THOMPSON, Jeffrey ANTHIS
  • Patent number: 9824889
    Abstract: Methods for depositing silicon include cycling dosing between 1 and 100 cycles of one or more first chlorosilane precursors on a III-V surface at a temperature between 300° C. and 500° C. to form a first layer. Methods may include desorbing chlorine from the first layer by treating the first layer with atomic hydrogen to form a second layer. Methods may include forming a silicon multilayer on the second layer by cycling dosing between 1 and 100 cycles of one or more second chlorosilane precursors and atomic hydrogen at a temperature between 300° C. and 500° C. A layered composition includes a first layer selected from the group consisting of InxGa1-xAs, InxGa1-xSb, InxGa1-xN, SiGe, and Ge, wherein X is between 0.1 and 0.99, and a second layer, wherein the second layer comprises Si—H and Si—OH.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: November 21, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Andrew C. Kummel, Mary Edmonds, Mei Chang, Jessica S. Kachian
  • Publication number: 20170288019
    Abstract: Semiconductor device stacks and devices made there from having Ge-rich device layers. A Ge-rich device layer is disposed above a substrate, with a p-type doped Ge etch suppression layer (e.g., p-type SiGe) disposed there between to suppress etch of the Ge-rich device layer during removal of a sacrificial semiconductor layer richer in Si than the device layer. Rates of dissolution of Ge in wet etchants, such as aqueous hydroxide chemistries, may be dramatically decreased with the introduction of a buried p-type doped semiconductor layer into a semiconductor film stack, improving selectivity of etchant to the Ge-rich device layers.
    Type: Application
    Filed: June 16, 2017
    Publication date: October 5, 2017
    Inventors: Willy RACHMADY, Van H. LE, Ravi PILLARISETTY, Jessica S. KACHIAN, Marc C. FRENCH, Aaron A. BUDREVICH
  • Patent number: 9773663
    Abstract: Embodiments described herein provide a self-limiting and saturating Si—Ox bilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO2, but instead produce a saturated Si—Ox film with —OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: September 26, 2017
    Assignees: Applied Materials, Inc., The Regents of the University of California
    Inventors: Jessica S. Kachian, Naomi Yoshida, Mei Chang, Mary Edmonds, Andrew C. Kummel, Sang Wook Park, Hyunwoong Kim
  • Patent number: 9768013
    Abstract: Methods and apparatus for processing a substrate are described herein. Methods for passivating dielectric materials include forming alkyl silyl moieties on exposed surfaces of the dielectric materials. Suitable precursors for forming the alkyl silyl moieties include (trimethylsilyl)pyrrolidine, aminosilanes, and dichlorodimethylsilane, among others. A capping layer may be selectively deposited on source/drain materials after passivation of the dielectric materials. Apparatus for performing the methods described herein include a platform comprising a transfer chamber, a pre-clean chamber, an epitaxial deposition chamber, a passivation chamber, and an atomic layer deposition chamber.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: September 19, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Abhishek Dube, Schubert S. Chu, Jessica S. Kachian, David Thompson, Jeffrey Anthis
  • Publication number: 20170194506
    Abstract: Deep gate-all-around semiconductor devices having germanium or group III-V active layers are described. For example, a non-planar semiconductor device includes a hetero-structure disposed above a substrate. The hetero-structure includes a hetero-junction between an upper layer and a lower layer of differing composition. An active layer is disposed above the hetero-structure and has a composition different from the upper and lower layers of the hetero-structure. A gate electrode stack is disposed on and completely surrounds a channel region of the active layer, and is disposed in a trench in the upper layer and at least partially in the lower layer of the hetero-structure. Source and drain regions are disposed in the active layer and in the upper layer, but not in the lower layer, on either side of the gate electrode stack.
    Type: Application
    Filed: March 21, 2017
    Publication date: July 6, 2017
    Inventors: Ravi Pillarisetty, Willy Rachmady, Van H. Le, Seung Hoon Sung, Jessica S. Kachian, Jack T. Kavalieros, Han Wui Then, Gilbert Dewey, Marko Radosavljevic, Benjamin Chu-Kung, Niloy Mukherjee