Patents by Inventor Jeung-In Lee

Jeung-In Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240004490
    Abstract: A display device includes a display panel, a touch sensing layer which is disposed on a first surface of the display panel and senses a touch input of a user, a first vibration device which is disposed on a second surface of the display panel and generates vibration according to driving voltages. The first vibration device generates a first vibration in response to a first touch input of the user to provide a first haptic feedback.
    Type: Application
    Filed: September 19, 2023
    Publication date: January 4, 2024
    Inventors: Dong Yeol YEOM, Jung Ho MYUNG, Min Jeung LEE, Se Ryun LEE
  • Patent number: 11809651
    Abstract: A display device includes a display panel, a touch sensing layer which is disposed on a first surface of the display panel and senses a touch input of a user, a first vibration device which is disposed on a second surface of the display panel and generates vibration according to driving voltages. The first vibration device generates a first vibration in response to a first touch input of the user to provide a first haptic feedback.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: November 7, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Yeol Yeom, Jung Ho Myung, Min Jeung Lee, Se Ryun Lee
  • Publication number: 20230201282
    Abstract: Provided is a composition for preventing and treating lipid-related metabolic diseases, the composition comprising, as an active ingredient, Lactobacillus plantarum ATG-K2 or Lactobacillus plantarum ATG-K6 isolated from fermented vegetables.
    Type: Application
    Filed: January 29, 2021
    Publication date: June 29, 2023
    Inventors: Hae-Jeung LEE, Eun-Jung PARK, Ji-Hee KANG, Hyun-Guh BAEK, Gun-Seok PARK
  • Publication number: 20230152341
    Abstract: A system for automating the processing of a sample for analysis includes a sample processing unit configured to manufacture a plurality of unit wafers by cutting an analysis target wafer and to manufacture a sample for analysis by applying at least one process to one of the plurality of unit wafers, a sample storage unit including a loading area having a plurality of reception holders, on which a unit wafer and the sample for analysis have been loaded, that are carried in and out, and a sample conveying unit configured to convey the analysis target wafer, the unit wafer, and the sample for analysis respectively between the sample processing unit and the sample storage unit.
    Type: Application
    Filed: November 10, 2022
    Publication date: May 18, 2023
    Inventors: Chan Hyuk RHEE, Jong Hee YOO, Kee Jeung LEE
  • Patent number: 11380952
    Abstract: This application relates to an energy storage device. In one embodiment, the energy storage device includes an electrode unit including first and second current collectors that are separated by a separator, first and second terminals respectively connected to the first and second current collectors and a case accommodating the electrode unit. The energy storage device also includes a flexible closure covering the case and having first and second through-holes passing therethrough and exposing the first and second terminals to the environment, wherein the flexible closure contains about 15 wt % or less of SiO2. According to some embodiments, since the weight percentage of SiO2 is significantly reduced and thus, the amount and degree of the SiO2 reduction significantly decreases, a structural deformation of the flexible closure at a microscopic level is minimized. Accordingly, a wetting phenomenon is significantly reduced, and thus the life span of an energy storage device significantly increases.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: July 5, 2022
    Assignee: Maxwell Technologies Korea Co., Ltd.
    Inventors: Jung-Hoon Chae, Na Ri Shin, Kyu Jeung Lee
  • Patent number: 11322501
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: May 3, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Patent number: 11217592
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: January 4, 2022
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Publication number: 20210373694
    Abstract: A display device includes a display panel, a touch sensing layer which is disposed on a first surface of the display panel and senses a touch input of a user, a first vibration device which is disposed on a second surface of the display panel and generates vibration according to driving voltages. The first vibration device generates a first vibration in response to a first touch input of the user to provide a first haptic feedback.
    Type: Application
    Filed: August 9, 2021
    Publication date: December 2, 2021
    Inventors: Dong Yeol YEOM, Jung Ho MYUNG, Min Jeung LEE, Se Ryun LEE
  • Patent number: 11086431
    Abstract: A display device includes a display panel, a touch sensing layer which is disposed on a first surface of the display panel and senses a touch input of a user, a first vibration device which is disposed on a second surface of the display panel and generates vibration according to driving voltages. The first vibration device generates a first vibration in response to a first touch input of the user to provide a first haptic feedback.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Yeol Yeom, Jung Ho Myung, Min Jeung Lee, Se Ryun Lee
  • Publication number: 20210028413
    Abstract: This application relates to an energy storage device. In one embodiment, the energy storage device includes an electrode unit including first and second current collectors that are separated by a separator, first and second terminals respectively connected to the first and second current collectors and a case accommodating the electrode unit. The energy storage device also includes a flexible closure covering the case and having first and second through-holes passing therethrough and exposing the first and second terminals to the environment, wherein the flexible closure contains about 15 wt % or less of SiO2. According to some embodiments, since the weight percentage of SiO2 is significantly reduced and thus, the amount and degree of the SiO2 reduction significantly decreases, a structural deformation of the flexible closure at a microscopic level is minimized. Accordingly, a wetting phenomenon is significantly reduced, and thus the life span of an energy storage device significantly increases.
    Type: Application
    Filed: March 12, 2019
    Publication date: January 28, 2021
    Inventors: Jung-Hoon Chae, Na Ri Shin, Kyu Jeung Lee
  • Publication number: 20200335505
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: July 1, 2020
    Publication date: October 22, 2020
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Patent number: 10734389
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: August 4, 2020
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Publication number: 20200241678
    Abstract: A display device includes a display panel, a touch sensing layer which is disposed on a first surface of the display panel and senses a touch input of a user, a first vibration device which is disposed on a second surface of the display panel and generates vibration according to driving voltages. The first vibration device generates a first vibration in response to a first touch input of the user to provide a first haptic feedback.
    Type: Application
    Filed: January 6, 2020
    Publication date: July 30, 2020
    Inventors: Dong Yeol YEOM, Jung Ho MYUNG, Min Jeung LEE, Se Ryun LEE
  • Patent number: 10658128
    Abstract: Disclosed herein is an electric double layer device including a urethane potting unit (50) for filling the gap between a portion of a first terminal (21) that is exposed out of a rubber cap (40) and a first through hole (41) and the gap between a portion of a second terminal (22) that is exposed out of the rubber cap and a second through hole (42), wherein an aluminum terminal (A) constituting each of the first terminal (21) and the second terminal (22) is anodized such that an aluminum oxide film (Al) is formed on the aluminum terminal, whereby the lifespan of the electric double layer device is relatively increased.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 19, 2020
    Assignee: Nesscap Co., Ltd.
    Inventors: Na Ri Shin, Sung Wook Yoo, Kyu Jeung Lee, Young Jin Kim, Hyung Sik Ahn, Jung Ho Choi, Young Seg Choi
  • Publication number: 20200152637
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Patent number: 10580777
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Publication number: 20200043933
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 6, 2020
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Patent number: 10483265
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: November 19, 2019
    Assignee: SK hynix Inc.
    Inventors: Jeong-Yeop Lee, Dong-Su Park, Jong-Bum Park, Sang-Do Lee, Jae-Min Lee, Kee-Jeung Lee, Jun-Soo Jang
  • Publication number: 20190131306
    Abstract: A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 2, 2019
    Inventors: Jeong-Yeop LEE, Dong-Su PARK, Jong-Bum PARK, Sang-Do LEE, Jae-Min LEE, Kee-Jeung LEE, Jun-Soo JANG
  • Patent number: 10127703
    Abstract: One or more embodiments of this disclosure provide an image output method. The image output method includes receiving image data for a plurality of image frames and caption data linked with the plurality of image frames. The method also includes outputting parsing the caption data to extract link information according to a data type from the caption data. The method also includes outputting a connection object or a list, for verifying the link information while the plurality of image frames are output on a display of the electronic device.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: November 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young Il Jung, Kwang Jeung Lee