Patents by Inventor Jhih-Bin CHEN

Jhih-Bin CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210273402
    Abstract: Various embodiments of the present disclosure are directed towards a method for forming a vertical cavity surface emitting laser (VCSEL) device. The method includes forming a bond bump and a bond ring over a substrate. A semiconductor die is bonded to the bond ring. A molding layer is formed around the semiconductor die. The molding layer is laterally offset from a cavity between the semiconductor die and the substrate. A VCSEL structure is formed over the bond bump.
    Type: Application
    Filed: May 17, 2021
    Publication date: September 2, 2021
    Inventors: Jhih-Bin Chen, Ming Chyi Liu
  • Publication number: 20210265344
    Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed over the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 26, 2021
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Alexander Kalnitsky, Kong-Beng Thei, Ming Chyi Liu, Shi-Chung Hsiao, Jhih-Bin Chen
  • Patent number: 11025033
    Abstract: Various embodiments of the present disclosure are directed towards a vertical cavity surface emitting laser (VCSEL) device. The VCSEL device includes a bond bump overlying a substrate. A VCSEL structure overlies the bond bump. The VCSEL structure includes a second reflector overlying an optically active region and a first reflector underlying the optically active region. A bond ring overlying the substrate and laterally separated from the bond bump. The bond ring continuously extends around the bond bump.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jhih-Bin Chen, Ming Chyi Liu
  • Publication number: 20210091538
    Abstract: In some embodiments, the present disclosure relates to a vertical cavity surface emitting laser (VCSEL) device that includes a microlens arranged over a reflector stack. The reflector stack comprises alternating reflector layers of a first material and a second material. The microlens stack includes a first lens layer, a second lens layer arranged over the first lens layer, and a third lens layer arranged over the second lens layer. The first lens layer comprises a first average concentration of a first element and has a first width. The second lens layer comprises a second average concentration of the first element greater than the first average concentration and has a second width smaller than the first width. The third lens layer comprises a third average concentration of the first element greater than the second average concentration and has a third width smaller than the second width.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 25, 2021
    Inventors: Jhih-Bin Chen, Ming Chyi Liu
  • Publication number: 20210066451
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a source region disposed within a substrate and a drain region disposed within the substrate. The drain region is separated from the source region along a first direction. A drift region is disposed within the substrate between the source region and the drain region, and a plurality of isolation structures are disposed within the drift region. A gate electrode is disposed within the substrate. The gate electrode has a base region disposed between the source region and the drift region and a plurality of gate extensions extending outward from a sidewall of the base region to over the plurality of isolation structures.
    Type: Application
    Filed: July 6, 2020
    Publication date: March 4, 2021
    Inventors: Jhih-Bin Chen, Ming Chyi Liu
  • Publication number: 20210028601
    Abstract: Some embodiments relate to a vertical cavity surface emitting laser (VCSEL) device including a VCSEL structure overlying a substrate. The VCSEL structure includes a first reflector, a second reflector, and an optically active region disposed between the first and second reflectors. A first spacer laterally encloses the second reflector. The first spacer comprises a first plurality of protrusions disposed along a sidewall of the second reflector.
    Type: Application
    Filed: October 14, 2020
    Publication date: January 28, 2021
    Inventors: Chen Yu Chen, Ming Chyi Liu, Jhih-Bin Chen
  • Publication number: 20200373732
    Abstract: Various embodiments of the present disclosure are directed towards a vertical cavity surface emitting laser (VCSEL) device. The VCSEL device includes a bond bump overlying a substrate. A VCSEL structure overlies the bond bump. The VCSEL structure includes a second reflector overlying an optically active region and a first reflector underlying the optically active region. A bond ring overlying the substrate and laterally separated from the bond bump. The bond ring continuously extends around the bond bump.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 26, 2020
    Inventors: Jhih-Bin Chen, Ming Chyi Liu
  • Patent number: 10847949
    Abstract: Some embodiments relate to a method for manufacturing a vertical cavity surface emitting laser. The method includes forming an optically active layer over a first reflective layer and forming a second reflective layer over the optically active layer. Forming a masking layer over the second reflective layer, where the masking layer leaves a sacrificial portion of the second reflective layer exposed. A first etch is performed to remove the sacrificial portion of the second reflective layer, defining a second reflector. Forming a first spacer covering outer sidewalls of the second reflector and masking layer. Performing an oxidation process to oxidize a peripheral region of the optically active layer. A second etch is performed to remove a portion of the oxidized peripheral region, defining an optically active region. Forming a second spacer covering outer sidewalls of the first spacer, the optically active region, and the first reflector.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen Yu Chen, Ming Chyi Liu, Jhih-Bin Chen
  • Publication number: 20200227369
    Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.
    Type: Application
    Filed: March 25, 2020
    Publication date: July 16, 2020
    Inventors: Jhih-Bin Chen, Chia-Shiung Tsai, Ming Chyi Liu, Eugene Chen
  • Patent number: 10643964
    Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.
    Type: Grant
    Filed: July 2, 2018
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jhih-Bin Chen, Chia-Shiung Tsai, Ming Chyi Liu, Eugene Chen
  • Publication number: 20200076162
    Abstract: Some embodiments relate to a method for manufacturing a vertical cavity surface emitting laser. The method includes forming an optically active layer over a first reflective layer and forming a second reflective layer over the optically active layer. Forming a masking layer over the second reflective layer, where the masking layer leaves a sacrificial portion of the second reflective layer exposed. A first etch is performed to remove the sacrificial portion of the second reflective layer, defining a second reflector. Forming a first spacer covering outer sidewalls of the second reflector and masking layer. An oxidation process is performed with the first spacer in place to oxidize a peripheral region of the optically active layer while leaving a central region of the optically active layer un-oxidized. A second etch is performed to remove a portion of the oxidized peripheral region, defining an optically active region.
    Type: Application
    Filed: September 5, 2018
    Publication date: March 5, 2020
    Inventors: Chen Yu Chen, Ming Chyi Liu, Jhih-Bin Chen
  • Publication number: 20200006271
    Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.
    Type: Application
    Filed: July 2, 2018
    Publication date: January 2, 2020
    Inventors: Jhih-Bin Chen, Chia-Shiung Tsai, Ming Chyi Liu, Eugene Chen
  • Patent number: 9353061
    Abstract: The present invention provides novel compounds of Formula (I), and pharmaceutically compositions thereof. Compounds of Formula (I) are inhibitors of histone deacetylases (HDACs) and 3-hydroxy-3-methylglutaryl coenzyme A (HMG-CoA) reductase (HMGR). Also provided are methods of using the compounds and pharmaceutical compositions for inhibiting the activity of HDACs and HMGR, treating diseases associated with HDACs or HMGR (e.g., cancer, hypercholesterolemia, an acute or chronic inflammatory disease, autoimmune disease, allergic disease, pathogen infection, neurodegenerative disease, and a disease associated with oxidative stress), or inhibiting drug resistance of cancer cells.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: May 31, 2016
    Assignees: ACADEMIA SINICA, NATIONAL TAIWAN UNIVERSITY
    Inventors: Jung-Hsin Lin, Jim-Min Fang, Ting-Rong Chern, Jhih-Bin Chen, Ching-Chow Chen, Tzu-Tang Wei
  • Patent number: 9115116
    Abstract: Disclosed herein are novel compounds of formula (I), and uses thereof. The compounds of Formula (I) are inhibitors of histone deacetylases (HDACs) and 3-hydroxy-3-methylglutaryl coenzyme A (HMG-CoA) reductase (HMGR). Also provided are methods of using the compounds of Formula (I) for inhibiting the activity of HDACs and HMGR, treating diseases associated with HDACs or HMGR (e.g.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: August 25, 2015
    Assignees: Academia Sinica, National Taiwan University
    Inventors: Jung-Hsin Lin, Ching-Chow Chen, Jim-Min Fang, Jhih-Bin Chen, Ting-Rong Chern, Tzu-Tang Wei
  • Publication number: 20150148360
    Abstract: The present invention provides novel compounds of Formula (I), and pharmaceutically compositions thereof. Compounds of Formula (I) are inhibitors of histone deacetylases (HDACs) and 3-hydroxy-3-methylglutaryl coenzyme A (HMG-CoA) reductase (HMGR). Also provided are methods of using the compounds and pharmaceutical compositions for inhibiting the activity of HDACs and HMGR, treating diseases associated with HDACs or HMGR (e.g., cancer, hypercholesterolemia, an acute or chronic inflammatory disease, autoimmune disease, allergic disease, pathogen infection, neurodegenerative disease, and a disease associated with oxidative stress), or inhibiting drug resistance of cancer cells.
    Type: Application
    Filed: July 19, 2013
    Publication date: May 28, 2015
    Inventors: Jung-Hsin Lin, Jim-Min Fang, Ting-Rong Chen, Jhih-Bin Chen, Ching-Chow Chen, Tzu-Tang Wei
  • Publication number: 20140206645
    Abstract: Disclosed herein are novel compounds of formula (I), and uses thereof. The compounds of Formula (I) are inhibitors of histone deacetylases (HDACs) and 3-hydroxy-3-methylglutaryl coenzyme A (HMG-CoA) reductase (HMGR). Also provided are methods of using the compounds of Formula (I) for inhibiting the activity of HDACs and HMGR, treating diseases associated with HDACs or HMGR (e.g.
    Type: Application
    Filed: January 21, 2014
    Publication date: July 24, 2014
    Applicants: National Taiwan University, Academia Sinica
    Inventors: Jung-Hsin LIN, Ching-Chow CHEN, Jim-Min FANG, Jhih-Bin CHEN, Ting-Rong CHERN, Tzu-Tang WEI