Patents by Inventor Ji Ae Park

Ji Ae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120164827
    Abstract: A through-silicon via fabrication method comprises forming a substrate by bonding the front surface of a silicon plate to a carrier using an adhesive layer therebetween to expose the back surface of the silicon plate. A silicon nitride passivation layer is deposited on the exposed back surface of the silicon plate of the substrate. A plurality of through holes are etched in the silicon plate, the through holes comprising sidewalls and bottom walls. A metallic conductor is deposited in the through holes to form a plurality of through-silicon vias.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Nagarajan RAJAGOPALAN, Ji Ae PARK, Ryan YAMASE, Shamik PATEL, Thomas NOWAK, Li-Qun XIA, Bok Hoen KIM, Ran DING, Jim BALDINO, Mehul NAIK, Sesh RAMASWAMI
  • Publication number: 20120128583
    Abstract: The present invention relates to DTPA derivatives capable of forming complexes by combining with metals and the like, metal complexes formed by combining with the DTPA derivatives, MR and CT contrast agents including gold (Au) nano-particles of which surfaces are coated with the metal complexes, and a method for manufacturing the same. The MR and CT contrast agents according to the present invention have a high magnetic relaxation rate, thereby providing an excellent contrast enforcement effect and a long image acquisition time. Furthermore, the MR and CT contrast agents are not toxic to the human body, and are image contrast agents of dual molecules capable of being applied to both MR and CT.
    Type: Application
    Filed: December 13, 2009
    Publication date: May 24, 2012
    Applicant: Kyungpook National University Industry Academic Cooperation Foundation
    Inventors: Tae Jung Kim, Yong Min Jang, Ji Ae Park
  • Patent number: 8076250
    Abstract: A layer stack of different materials is deposited on a substrate in a single plasma enhanced chemical vapor deposition processing chamber while maintaining a vacuum. A substrate is placed in the processing chamber and a first processing gas is used to form a first layer of a first material on the substrate. A plasma purge and gas purge are performed before a second processing gas is used to form a second layer of a second material on the substrate. The plasma purge and gas purge are repeated and the additional layers of first and second materials are deposited on the layer stack.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: December 13, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Nagarajan Rajagopalan, Xinhai Han, Ji Ae Park, Tsutomu Kiyohara, Sohyun Park, Bok Hoen Kim
  • Publication number: 20110223765
    Abstract: A method of forming a passivation layer comprising silicon nitride on features of a substrate is described. In a first stage of the deposition method, a dielectric deposition gas, comprising a silicon-containing gas and a nitrogen-containing gas, is introduced into the process zone and energized to deposit a silicon nitride layer. In a second stage, a treatment gas, having a different composition than that of the dielectric deposition gas, is introduced into the process zone and energized to treat the silicon nitride layer. The first and second stages can be performed a plurality of times.
    Type: Application
    Filed: March 15, 2010
    Publication date: September 15, 2011
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Nagarajan RAJAGOPALAN, Xinhai HAN, Ryan YAMASE, Ji Ae PARK, Shamik PATEL, Thomas NOWAK, Zhengjiang "David" CUI, Mehul NAIK, Heung Lak PARK, Ran DING, Bok Hoen KIM
  • Publication number: 20110136327
    Abstract: Methods of forming high-current density vertical p-i-n diodes on a substrate are described. The methods include the steps of concurrently combining a group-IV-element-containing precursor with a sequential exposure to an n-type dopant precursor and a p-type dopant precursor in either order. An intrinsic layer is deposited between the n-type and p-type layers by reducing or eliminating the flow of the dopant precursors while flowing the group-IV-element-containing precursor. The substrate may reside in the same processing chamber during the deposition of each of the n-type layer, intrinsic layer and p-type layer and the substrate is not exposed to atmosphere between the depositions of adjacent layers.
    Type: Application
    Filed: June 25, 2010
    Publication date: June 9, 2011
    Applicant: Applied Materials, Inc.
    Inventors: Xinhai Han, Nagarajan Rajagopalan, Ji Ae Park, Bencherki Mebarki, Heung Lak Park, Bok Hoen Kim