Patents by Inventor Ji Cui

Ji Cui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250254575
    Abstract: Embodiments relate to a method and apparatus for a soft satellite switching procedure. A method for a user equipment (UE) in communication with a source satellite to switch to a target satellite includes the following operations: receiving a signal from the source satellite; and determining whether to switch to the target satellite based upon a hard switch or a soft switch.
    Type: Application
    Filed: September 28, 2023
    Publication date: August 7, 2025
    Inventors: Fangli XU, Ji CUI, Dawei ZHANG, Yuqin CHEN, Chunhai YAO, Haijing HU, Chunxuan YE, Yang TANG, Wei ZENG
  • Publication number: 20250246507
    Abstract: A semiconductor device includes a first interconnect structure, a device layer, a second interconnect structure, a diamond layer, a passivation layer, and an electrical connector. The device layer is disposed over the first interconnect structure. The second interconnect structure is disposed over the device layer and comprises a topmost metallization pattern. The diamond layer is disposed over the second interconnect structure and at least revealing a part of the topmost metallization pattern. The passivation layer covers the diamond layer and reveals the part of the topmost metallization pattern. The electrical connector is disposed over the passivation layer and bonded to the part of the topmost metallization pattern.
    Type: Application
    Filed: January 29, 2024
    Publication date: July 31, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Han-Jong Chia, Yu-Jen Lien, Ke-Han Shen, Cheng-Chieh Hsieh, Kuo-Chung Yee, Szu-Wei Lu, Chung-Ju Lee, Chen-Hua Yu, Ji CUI, Chih-Ming Ke, Hung-Yi Kuo
  • Publication number: 20250234593
    Abstract: A semiconductor structure and a formation method are provided. The semiconductor structure includes a first transistor, and the first transistor includes a first channel layer and a first gate structure. The semiconductor transistor further includes a second transistor. The second transistor includes a second channel layer and a second gate structure. The semiconductor transistor further includes a bonding structure vertically sandwiched between the first transistor and the second transistor. The bonding structure includes a first dielectric bonding layer attached to the first gate structure and a first conductive bonding structure formed through the first dielectric bonding layer. The bonding structure further includes a second dielectric bonding layer attached to the first dielectric bonding layer and the second gate structure and a second conductive bonding structure formed through the second dielectric bonding layer and bonded to the first conductive bonding structure.
    Type: Application
    Filed: January 16, 2024
    Publication date: July 17, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Han-Jong Chia, Ji Cui
  • Patent number: 12359090
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: July 15, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Chi-Jen Liu, Chih-Chieh Chang, Kao-Feng Liao, Peng-Chung Jangjian, Chun-Wei Hsu, Ting-Hsun Chang, Liang-Guang Chen, Kei-Wei Chen, Hui-Chi Huang
  • Patent number: 12297375
    Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: May 13, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Chi-Jen Liu, Liang-Guang Chen, Kei-Wei Chen, Chun-Wei Hsu, Li-Chieh Wu, Peng-Chung Jangjian, Kao-Feng Liao, Fu-Ming Huang, Wei-Wei Liang, Tang-Kuei Chang, Hui-Chi Huang
  • Publication number: 20250038073
    Abstract: A package structure and a method for forming the same are provided. The package structure includes a first package structure and a second package structure. The first package structure includes a first device formed over a first substrate. The first device includes a first conductive plug connected to a through substrate via (TSV) structure formed in the first substrate. A buffer layer surrounds the first substrate. A first bonding layer is formed over the first substrate and the buffer layer. The second package structure includes a second device formed over a second substrate. A second bonding layer is formed over the second device. A hybrid bonding structure is between the first package structure and the second package structure by bonding the first bonding layer to the second bonding layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ke-Han SHEN, Chih-Yuan CHEN, Jiung WU, Hung-Yi Kuo, Chung-Ju LEE, Tung-He CHOU, Ji CUI, Kuo-Chung YEE, Chen-Hua YU, Cheng-Chieh HSIEH, Yu-Jen LIEN, Yian-Liang KUO, Shih-Hao TSENG, Jen Yu WANG, Tzu-Chieh Chou
  • Publication number: 20240379421
    Abstract: A semiconductor structure includes: a first conductive layer arranged over a substrate; a dielectric layer arranged over the first conductive layer; a second conductive layer arranged within the dielectric layer and electrically connected to the first conductive layer, the second conductive layer including a sidewall distant from the dielectric layer by a width; and a first blocking layer over a surface of the first conductive layer between the second conducive layer and the dielectric layer. The first blocking layer includes at least one element of a precipitant.
    Type: Application
    Filed: July 21, 2024
    Publication date: November 14, 2024
    Inventors: CHUN-WEI HSU, CHIH-CHIEH CHANG, YI-SHENG LIN, JIAN-CI LIN, JENG-CHI LIN, TING-HSUN CHANG, LIANG-GUANG CHEN, JI CUI, KEI-WEI CHEN, CHI-JEN LIU
  • Publication number: 20240363361
    Abstract: A semiconductor processing tool includes a cleaning chamber configured to perform a post-chemical mechanical polishing/planarization (post-CMP) cleaning operation in an oxygen-free (or in a near oxygen-free) manner. An inert gas may be provided into the cleaning chamber to remove oxygen from the cleaning chamber such that the post-CMP cleaning operation may be performed in an oxygen-free (or in a near oxygen-free) environment. In this way, the post-CMP cleaning operation may be performed in an environment that may reduce oxygen-causing corrosion of metallization layers and/or metallization structures on and/or in the semiconductor wafer, which may increase semiconductor processing yield, may decrease semiconductor processing defects, and/or may increase semiconductor processing quality, among other examples.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Ji CUI, Chih Hung CHEN, Liang-Guang CHEN, Kei-Wei CHEN
  • Publication number: 20240363404
    Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.
    Type: Application
    Filed: July 9, 2024
    Publication date: October 31, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng CHEN, Tang-Kuei CHANG, Yee-Chia YEO, Huicheng CHANG, Wei-Wei LIANG, Ji CUI, Fu-Ming HUANG, Kei-Wei CHEN, Liang-Yin CHEN
  • Patent number: 12131944
    Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Hsu, Chih-Chieh Chang, Yi-Sheng Lin, Jian-Ci Lin, Jeng-Chi Lin, Ting-Hsun Chang, Liang-Guang Chen, Ji Cui, Kei-Wei Chen, Chi-Jen Liu
  • Publication number: 20240290629
    Abstract: A method for CMP includes following operations. A first metal layer and a second metal layer are formed in a dielectric structure. The second metal layer is formed over a portion of the first metal layer. A first composition is provided to remove a portion of the first metal layer. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed to expose the second metal layer. A CMP operation is performed to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure.
    Type: Application
    Filed: April 29, 2024
    Publication date: August 29, 2024
    Inventors: JI CUI, FU-MING HUANG, TING-KUI CHANG, TANG-KUEI CHANG, CHUN-CHIEH LIN, WEI-WEI LIANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUNG YEN, TING-HSUN CHANG, CHI-HSIANG SHEN, LI-CHIEH WU, CHI-JEN LIU
  • Patent number: 12068169
    Abstract: A semiconductor processing tool includes a cleaning chamber configured to perform a post-chemical mechanical polishing/planarization (post-CMP) cleaning operation in an oxygen-free (or in a near oxygen-free) manner. An inert gas may be provided into the cleaning chamber to remove oxygen from the cleaning chamber such that the post-CMP cleaning operation may be performed in an oxygen-free (or in a near oxygen-free) environment. In this way, the post-CMP cleaning operation may be performed in an environment that may reduce oxygen-causing corrosion of metallization layers and/or metallization structures on and/or in the semiconductor wafer, which may increase semiconductor processing yield, may decrease semiconductor processing defects, and/or may increase semiconductor processing quality, among other examples.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: August 20, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ji Cui, Chih Hung Chen, Liang-Guang Chen, Kei-Wei Chen
  • Patent number: 12002684
    Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Publication number: 20230364733
    Abstract: A chemical mechanical planarization apparatus includes a multi-zone platen comprising a plurality of individually controlled concentric toroids. The rotation direction, rotation speed, applied force, relative height, and temperature of each concentric toroid is individually controlled. Concentric polishing pads are affixed to an upper surface of each of the individually controlled concentric toroids. The chemical mechanical planarization apparatus includes a single central slurry source or includes individual slurry sources for each individually controlled concentric toroid.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 16, 2023
    Inventors: Ting-Hsun Chang, Hung Yen, Chi-Hsiang Shen, Fu-Ming Huang, Chun-Chieh Lin, Tsung Hsien Chang, Ji Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
  • Patent number: 11772228
    Abstract: A chemical mechanical planarization apparatus includes a multi-zone platen comprising a plurality of individually controlled concentric toroids. The rotation direction, rotation speed, applied force, relative height, and temperature of each concentric toroid is individually controlled. Concentric polishing pads are affixed to an upper surface of each of the individually controlled concentric toroids. The chemical mechanical planarization apparatus includes a single central slurry source or includes individual slurry sources for each individually controlled concentric toroid.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: October 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ting-Hsun Chang, Hung Yen, Chi-Hsiang Shen, Fu-Ming Huang, Chun-Chieh Lin, Tsung Hsien Chang, Ji Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
  • Patent number: 11718812
    Abstract: A cleaning composition for cleaning a surface of a substrate comprising silicon germanium after a chemical mechanical polishing process is provided. The cleaning composition includes an oligomeric or polymeric polyamine, at least one wetting agent, a pH adjusting agent, and a solvent.
    Type: Grant
    Filed: March 3, 2021
    Date of Patent: August 8, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ji Cui, William Weilun Hong, Gin-Chen Huang, Shich-Chang Suen, Kei-Wei Chen
  • Patent number: 11658065
    Abstract: A method for CMP includes following operations. A metal layer is received. A CMP slurry composition is provided in a CMP apparatus. The CMP slurry composition includes at least a first oxidizer and a second oxidizer different from each other. The first oxidizer is oxidized to form a peroxidant by the second oxidizer. A portion of the metal layer is oxidized to form a first metal oxide by the peroxidant. The first metal oxide is re-oxidized to form a second metal oxide by the second oxidizer.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Chi-Hsiang Shen, Ting-Hsun Chang, Li-Chieh Wu, Hung Yen, Chi-Jen Liu, Liang-Guang Chen, Kei-Wei Chen
  • Publication number: 20230082084
    Abstract: A method for CMP includes following operations. A metal stack is received. The metal layer stack includes at least a first metal layer and a second metal layer, and a top surface of the first metal layer and a top surface of the second metal layer are exposed. A protecting layer is formed over the second metal layer. A portion of the first metal layer is etched. The protecting layer protects the second metal layer during the etching of the portion of the first metal layer. A top surface of the etched first metal layer is lower than a top surface of the protecting layer. The protecting layer is removed from the second metal layer.
    Type: Application
    Filed: November 21, 2022
    Publication date: March 16, 2023
    Inventors: JI CUI, FU-MING HUANG, TING-KUI CHANG, TANG-KUEI CHANG, CHUN-CHIEH LIN, WEI-WEI LIANG, LIANG-GUANG CHEN, KEI-WEI CHEN, HUNG YEN, TING-HSUN CHANG, CHI-HSIANG SHEN, LI-CHIEH WU, CHI-JEN LIU
  • Patent number: 11597854
    Abstract: The invention relates to a chemical-mechanical polishing composition comprising (a) a first abrasive comprising cationically modified colloidal silica particles, (b) a second abrasive having a Mohs hardness of about 5.5 or more, (c) a cationic polymer, (d) an iron containing activator, (e) an oxidizing agent, and (f) water. The invention also relates to a method of chemically mechanically polishing a substrate, especially a substrate comprising tungsten and barrier layers (e.g., nitrides), with the polishing composition.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: March 7, 2023
    Assignee: CMC Materials, Inc.
    Inventors: William J. Ward, Matthew E. Carnes, Ji Cui, Helin Huang
  • Publication number: 20230064918
    Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Inventors: CHUN-WEI HSU, CHIH-CHIEH CHANG, YI-SHENG LIN, JIAN-CI LIN, JENG-CHI LIN, TING-HSUN CHANG, LIANG-GUANG CHEN, JI CUI, KEI-WEI CHEN, CHI-JEN LIU