Abstract: A memory device includes a memory cell connected to a word line and a bit line, a row driver that drives the word line to a precharge level, a column driver that drives the bit line to a first target level, a sense amplifier that senses a first sensing level of the word line after the first target level is applied to the memory cell, and a read control circuit that controls the column driver so that a second target level different from the first target level is selectively applied to the memory cell depending on the first sensing level sensed by the sense amplifier.

Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.

Abstract: Provided is a battery module for a secondary battery. The battery module includes a busbar for a connection of electrode tabs. According to exemplary embodiments of the present disclosure, in a battery module for a secondary battery, a thickness of a welded portion may be reduced while maintaining a total cross-sectional area of a busbar when electrode tabs of each of secondary batteries are connected in series or in parallel by a laser welding. Thus, the battery module may have an enhanced welding quality, and also may have an effect of being applicable to a high-capacity battery or a battery that is used for a long period of time.

Abstract: A battery module may include a plurality of sub-modules arranged in a single direction, a cooling unit contacting one sides of the plurality of sub-modules to cool the plurality of sub-modules, and a heating unit contacting other sides opposing the one sides of the plurality of sub-modules to heat the plurality of sub-modules.

Abstract: Disclosed herein are a multi-cell tab cutting apparatus for a plurality of cells, which have a plurality of tabs formed at one side, and a method therefor. The multi-cell tab cutting apparatus includes a base frame, a cell tab fixer connected to the base frame and configured to fix and support the plurality of tabs, and a cutter positioned at the base frame and configured to cut the plurality of tabs through driving.

Abstract: Provided is a battery module, and more particularly, a battery module capable of improving cooling efficiency of battery cells and uniformly cooling the battery cells by reducing a contact resistance between a cooling fin and a heat sink, by allowing the cooling fin to be coupled and fixed to the heat sink so that the cooling fin which is in contact with the battery cell to conduct heat is in close contact with the heat sink for radiating the heat.

Abstract: A memory device includes a memory cell connected to a word line and a bit line, a row driver that drives the word line to a precharge level, a column driver that drives the bit line to a first target level, a sense amplifier that senses a first sensing level of the word line after the first target level is applied to the memory cell, and a read control circuit that controls the column driver so that a second target level different from the first target level is selectively applied to the memory cell depending on the first sensing level sensed by the sense amplifier.

Abstract: A nonvolatile memory device includes a differential current driver that receives a first differential signal and a second differential signal, which are based on a temperature, and generates a first compensation current and a second compensation current corresponding to a difference value between the first and second differential signals. A current mirror circuit copies a first current, which is a sum of a reference current and the first compensation current, to generate a second current having a same value as a value of the first current and regulates the reference current depending on a difference value of the second current and the second compensation current. A trimming circuit generates a program current or a read current based on the regulated reference current.

Abstract: A battery module may include a plurality of sub-modules arranged in a single direction, a cooling unit contacting one sides of the plurality of sub-modules to cool the plurality of sub-modules, and a heating unit contacting other sides opposing the one sides of the plurality of sub-modules to heat the plurality of sub-modules.

Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.

Abstract: A memory device may include a memory cell array including a plurality of memory cells and a compensation resistor electrically connected to the memory cell array. The compensation resistor may generate a cell current compensating for a voltage drop generated in a parasitic resistor of a signal line connected to at least one memory cell of the plurality of memory cells. The compensation circuit may control a magnitude of resistance of a compensation resistor upon receiving an address corresponding to the memory cell. The compensation circuit may increase a magnitude of the cell current based on adjusting the magnitude of resistance of the compensation resistor to be substantially equal to a resistance value of the parasitic resistor.

Abstract: A circuit may include a transmitter for generating a signal indicative of input data, an on-chip channel for transmitting the signal from the transmitter, and a receiver comprising a receiving terminal that has a negative resistance value as input resistance of the receiving terminal, the receiver generating a signal indicative of recovered data based on the transmitted signal through the on-chip channel. The circuit may recycle a portion of charge stored in the on-chip channel using charge recycling, and the charge recycling is associated with the negative resistance value of the input resistance.

Abstract: A circuit may include a transmitter for generating a signal indicative of input data, an on-chip channel for transmitting the signal from the transmitter, and a receiver comprising a receiving terminal that has a negative resistance value as input resistance of the receiving terminal, the receiver generating a signal indicative of recovered data based on the transmitted signal through the on-chip channel. The circuit may recycle a portion of charge stored in the on-chip channel using charge recycling, and the charge recycling is associated with the negative resistance value of the input resistance.

Abstract: An integrated circuit test apparatus includes: a first test unit configured to output a current for a built-in self test (BIST) progress state for each internal circuit of an integrated circuit in a BIST test mode and to determine whether each internal circuit operates normally in a wake-up mode of the integrated circuit; and a first determination module configured to determine whether each internal circuit is in a stuck state based on a change detected by the first test unit.

Abstract: A nonvolatile memory device includes a bank and a program current generator. The bank includes a memory cell array that includes phase change memory cells storing data based on a program current, and the transfer element transfers the program current to the memory cell array through current mirroring. The program current generator generates the program current based on a reference current.

Abstract: A compensation circuit may include a reference current generating circuit including a first transistor of a first width configured to transfer a first current. The reference generating circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generating circuit including a second transistor of a second width configured to transfer a second current. The second transistor may be selected from among a first group of transistors based on a code. The transistors of the first group may have widths proportional to the first width. The compensation current generating circuit may output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage having a magnitude based on a magnitude of the second current and the second width.

Abstract: A real-time slope control apparatus includes power-train transistors coupled between a power terminal and an output node and turned on in response to an error signal, a voltage regulator, a comparator configured to compare whether the feedback voltage and a sub-reference voltage match each other, pull-up transistors coupled between the power terminal and the output node and sequentially turned on in response to first control signals corresponding to a comparison result value of the comparator, and pull-down transistors coupled between the output node and the ground terminal and sequentially turned on in response to second control signals corresponding to the comparison result value of the comparator.

Abstract: A memory device may include a memory cell array including a plurality of memory cells and a compensation resistor electrically connected to the memory cell array. The compensation resistor may generate a cell current compensating for a voltage drop generated in a parasitic resistor of a signal line connected to at least one memory cell of the plurality of memory cells. The compensation circuit may control a magnitude of resistance of a compensation resistor upon receiving an address corresponding to the memory cell. The compensation circuit may increase a magnitude of the cell current based on adjusting the magnitude of resistance of the compensation resistor to be substantially equal to a resistance value of the parasitic resistor.

Abstract: A compensation circuit may include a reference current generating circuit including a first transistor of a first width configured to transfer a first current. The reference generating circuit may output a reference current based on the first current. The compensation circuit may include a compensation current generating circuit including a second transistor of a second width configured to transfer a second current. The second transistor may be selected from among a first group of transistors based on a code. The transistors of the first group may have widths proportional to the first width. The compensation current generating circuit may output a compensation current having a magnitude selected proportionally to a magnitude of the reference current based on the second current. The compensation circuit may include a current mirror circuit configured to output a compensation voltage having a magnitude based on a magnitude of the second current and the second width.

Abstract: Provided is a battery module, and more particularly, a battery module capable of improving cooling efficiency of battery cells and uniformly cooling the battery cells by reducing a contact resistance between a cooling fin and a heat sink, by allowing the cooling fin to be coupled and fixed to the heat sink so that the cooling fin which is in contact with the battery cell to conduct heat is in close contact with the heat sink for radiating the heat.