Abstract: A hinge device in a portable terminal is provided, in which a first driving cam is fixed to one end of a hinge shaft by a locking device, for rotating, a second driving cam is provided at the other end of the hinge shaft, for rotating together with the first driving cam and making a linear reciprocal motion along the hinge shaft, a driven cam is interposed between the first and second driving cams, for making a linear reciprocal motion along the hinge shaft as a cam motion with the first and second driving cams, and an elastic member is interposed between a hinge housing and the second driving cam.

Abstract: A three-dimensional graphene structure, and methods of manufacturing and transferring the same including forming at least one layer of graphene having a periodically repeated three-dimensional shape. The three-dimensional graphene structure is formed by forming a pattern having a three-dimensional shape on a surface of a substrate, and forming the three-dimensional graphene structure having the three-dimensional shape of the pattern by growing graphene on the substrate on which the pattern is formed. The three-dimensional graphene structure is transferred by injecting a gas between the three-dimensional graphene structure and the substrate, separating the three-dimensional graphene structure from the substrate by bonding the three-dimensional graphene structure to an adhesive support, combining the three-dimensional graphene structure with an insulating substrate, and removing the adhesive support.

Abstract: Provided is a portable communication device including a first housing, a second housing rotatably coupled with the first housing, and a hinge portion provided between the first housing and the second housing to stepwise rotate the second housing toward or away from the first housing, in which display units are disposed on inner and outer sides of the first housing and the second housing, respectively, such that the display units on the inner and outer surfaces of the housings may be used independently or in conjunction to provide for larger display screens.

Abstract: The present invention provides an automated toe adjustment apparatus and method that includes a power nut runner, a vision machine, a robot, and a floating mechanism. More particularly, the power nut runner adjusts a toe by adjusting an adjusting bolt of the tie-rod assembly. The vision machine photographs the power nut runner to verify position information of the power nut runner. The robot engages the power nut runner with the adjusting bolt of the tie-rod assembly and rotates the power nut runner. The floating mechanism absorbs a shock between the power nut runner and the robot as the vehicle is shaken by the overall process.

Abstract: The present invention provides an automated steering wheel leveling system and method. Particularly, the automated steering wheel leveling system includes a machine vision, a plurality of motor cylinders, a motor, and a robot, each operated by a process PC. The machine vision photographs a steering wheel to obtain position information of the steering wheel and determines a stroke of a motor cylinder and a grip position of a gripper using the position information. The plurality of motor cylinders move a plurality of grippers to steering wheel to secure the steering wheel. The motor rotates the steering wheel in order to adjust a zero-point of the steering wheel. The robot then moves the machine vision, the motor cylinder, and the motor to the steering wheel to align a shaft of the servo motor with a shaft of the steering wheel.

Abstract: A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.

Abstract: A nonvolatile memory device includes a device isolation film defining an active region in a semiconductor substrate, a pocket well region formed in an upper portion of the active region and having a first conductivity type, a gate electrode formed on the active region and extending to intersect the active region, a tunnel insulating film, a charge storage film, and a blocking insulating film sequentially disposed between the active region and the gate electrode, a source region and a drain region respectively formed in a first region and a second region of the active region exposed on both sides of the gate electrode, and each having a second conductivity type opposite to the first conductivity type, a pocket well junction region formed in the first region adjacent to the source region and contacting the pocket well region, and having the first conductivity type, and a metal silicide layer formed in the first region and contacting the source region and the pocket well junction region.

Abstract: Provided is a semiconductor device. The semiconductor device includes a lower active region on a semiconductor substrate. A plurality of upper active regions protruding from a top surface of the lower active region and having a narrower width than the lower active region are provided. A lower isolation region surrounding a sidewall of the lower active region is provided. An upper isolation region formed on the lower isolation region, surrounding sidewalls of the upper active regions, and having a narrower width than the lower isolation region is provided. A first impurity region formed in the lower active region and extending into the upper active regions is provided. Second impurity regions formed in the upper active regions and constituting a diode together with the first impurity region are provided. A method of fabricating the same is provided as well.

Abstract: According to a precise critical temperature indicator and a control method thereof of the present invention, the precise critical temperature indicator comprises as one body: a blocking boundary layer which is positioned between a spreading material member including an operation button and spreading medium members including a spreadable area for a spreading material; and a temperature sensor which is controlled and operated as the spreading material passes through the blocking boundary layer and contacts the spreading medium member according to a user's pressing of the operation button. As a result, operation of the temperature sensor is easily controlled using the operation button. Also, the precise critical temperature indicator does not require a process of cooling a product down to below a critical temperature before using the product, due to the hermetic sealing of the spreading material member.

Abstract: A precise critical temperature indicator is applied to small products requiring refrigeration or freezing to control the operation of a temperature sensor built into an integrated structure of a single body. A method for manufacturing said precise critical temperature indicator, wherein a plurality of development medium members and a plurality of development material members are opposed to each other, and blocking members are interposed therebetween to support the development medium members and the development material members separately from each other, the development medium members are provided with paths for moving development materials, or paths for movement of development materials can be shortened to adjust speed, and an indication unit is arranged to indicate the state of the development materials at an end or central portion of the development medium when the development materials are exposed to a critical temperature for a predetermined time period.

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract: Provided is a handover control device and method of a multi-mode mobile communication terminal. The device includes a first processing module; a second processing module connected in its inter-chip path with the first processing module; and an application processor for controlling the first processing module to transmit an IMSI (international mobile subscriber identity) to the second processing module when a traffic handover event from a first mode to a second mode occurs.

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.

Abstract: A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.

Abstract: A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

Abstract: A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

Abstract: A non-volatile memory device includes an upwardly protruding fin disposed on a substrate and a control gate electrode crossing the fin. A floating gate is interposed between the control gate electrode and the fin and includes a first storage gate and a second storage gate. The first storage gate is disposed on a sidewall of the fin, and the second storage gate is disposed on a top surface of the fin and is connected to the first storage gate. A first insulation layer is interposed between the first storage gate and the sidewall of the fin, and a second insulation layer is interposed between the second storage gate and the top surface of the fin. The second insulation layer is thinner than the first insulation layer. A blocking insulation pattern is interposed between the control gate electrode and the floating gate.

Abstract: A method of manufacturing a nonvolatile memory device is provided. The method includes forming an isolation layer in a semiconductor substrate defining an active region and forming a molding pattern on the isolation layer. A first conductive layer is formed on a sidewall and a top surface of the molding pattern and on the semiconductor substrate. The first conductive layer on the top surface of the molding pattern is selectively removed forming a conductive pattern. The conductive pattern includes a body plate disposed on the active region and a protrusion which extends from an edge of the body plate onto the sidewall of the molding pattern. The molding pattern is then removed. An inter-gate dielectric layer is formed on the isolation layer and the conductive pattern. Nonvolatile memory devices manufactured using the method are also provided.

Abstract: Provided is an EEPROM device and a method of manufacturing the same. The EEPROM device is composed of one cell including a memory transistor and a selection transistor located in series on a semiconductor substrate, and includes a source region located on a side region of a memory transistor, a drain region located on one side region of the selection transistor facing the source region, and a floating junction region formed between the memory transistor and the selection transistor, wherein the floating junction region includes a first doped region extended toward the source region under a region occupied by the memory transistor and a second doped region doped with the opposite conductive dopant to the first doped region and formed to surround the first doped region.

Abstract: A semiconductor device includes a device isolation layer on a semiconductor substrate defining an active region in the semiconductor substrate, a low voltage well of a first conductivity type in the active region of the semiconductor substrate, a high voltage impurity region of a second conductivity type in the active region of the semiconductor substrate, the high voltage impurity region positioned in an upper portion of the low voltage well, a high concentration impurity region of the second conductivity type within the high voltage impurity region and spaced apart from the device isolation layer, and a floating impurity region of the first conductivity type between the device isolation layer and the high concentration impurity region, the floating impurity region being a portion of an upper surface of the active region.