Patents by Inventor Ji Hwang Kim
Ji Hwang Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220045033Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.Type: ApplicationFiled: October 25, 2021Publication date: February 10, 2022Inventors: HYOEUN KIM, JI HWANG KIM, JISUN YANG, SEUNGHOON YEON, CHAJEA JO, SANG-UK HAN
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Patent number: 11227855Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.Type: GrantFiled: May 9, 2019Date of Patent: January 18, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jang-woo Lee, Un-byoung Kang, Ji-hwang Kim, Jong-bo Shim, Young-kun Jee
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Publication number: 20210343617Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.Type: ApplicationFiled: July 15, 2021Publication date: November 4, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Hwang KIM, Jong Bo SHIM, Jang Woo LEE, Yung Cheol KONG, Young Hoon HYUN
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Patent number: 11158603Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.Type: GrantFiled: March 11, 2019Date of Patent: October 26, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Hyoeun Kim, Ji Hwang Kim, Jisun Yang, Seunghoon Yeon, Chajea Jo, Sang-Uk Han
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Patent number: 11152416Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.Type: GrantFiled: July 10, 2019Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwang Kim, Chajea Jo, Hyoeun Kim, Jongbo Shim, Sang-Uk Han
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Patent number: 11069592Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.Type: GrantFiled: September 25, 2019Date of Patent: July 20, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hwang Kim, Jong Bo Shim, Jang Woo Lee, Yung Cheol Kong, Young Hoon Hyun
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Publication number: 20210202563Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: ApplicationFiled: March 16, 2021Publication date: July 1, 2021Inventors: Ji-hwang KIM, Jong-bo SHIM, Sang-uk HAN, Cha-jea JO, Won-il LEE
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Publication number: 20210183757Abstract: A semiconductor package includes a lower package, an interposer on the lower package, and an under-fill layer between the interposer and the lower package. The interposer includes a through hole that vertically penetrates the interposer. The under-fill layer includes an extension that fills at least a portion of the through hole.Type: ApplicationFiled: September 10, 2020Publication date: June 17, 2021Inventors: JI HWANG KIM, Hyunkyu Kim, Jongbo Shim, Eunhee Jung, Kyoungsei Choi
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Patent number: 11018173Abstract: An image sensor including: a semiconductor substrate having a first region and a second region; an isolation region filling an isolation trench that partially penetrates the semiconductor substrate; a plurality of photoelectric conversion regions defined by the isolation region and forming a first hexagonal array on a plane that is parallel to a surface of the semiconductor substrate; and a plurality of microlenses respectively corresponding to the plurality of photoelectric conversion regions, and forming a second hexagonal array on the plane that is parallel to the surface of the semiconductor substrate.Type: GrantFiled: January 18, 2019Date of Patent: May 25, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-hwang Kim, Kyung-suk Oh
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Patent number: 10978431Abstract: A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.Type: GrantFiled: February 27, 2019Date of Patent: April 13, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jongbo Shim, Ji Hwang Kim, Chajea Jo, Sang-Uk Han
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Patent number: 10971535Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.Type: GrantFiled: June 29, 2017Date of Patent: April 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-hwang Kim, Jong-bo Shim, Sang-uk Han, Cha-jea Jo, Won-il Lee
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Patent number: 10923428Abstract: A semiconductor package includes a substrate, a semiconductor chip mounted on the substrate, an interposer chip on the semiconductor chip and including a redistribution pattern, a first pad on the interposer chip, a second pad on the interposer chip and spaced apart from the first pad, and a bonding wire electrically connected to the second pad and the first substrate. The second pad is electrically connected through the redistribution pattern to the first pad. The footprint of the interposer chip is greater than the footprint of the first semiconductor chip.Type: GrantFiled: June 5, 2019Date of Patent: February 16, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hwang Kim, Kilsoo Kim, Jongbo Shim, Jangwoo Lee, Eunhee Jung
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Publication number: 20210043612Abstract: A semiconductor package device may include a first package substrate, a first semiconductor chip on the first package substrate, an interposer on the first semiconductor chip, a warpage prevention member on the interposer, a molding member on the interposer and the first package substrate, and a second package substrate on the molding member. At least a portion of a top surface of the molding member may be spaced apart from a bottom surface of the second package substrate.Type: ApplicationFiled: April 10, 2020Publication date: February 11, 2021Inventors: JANGWOO LEE, JONGBO SHIM, JI HWANG KIM, YUNGCHEOL KONG, YOUNGBAE KIM, TAEHWAN KIM, HYUNGLAK MA
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Patent number: 10750112Abstract: A substrate structure for an image sensor module includes a module substrate including a sensor mounting hole, a reinforcing plate on a lower surface of the module substrate, an image sensor chip on the reinforcing plate within the sensor mounting hole, and a reinforcing pattern in the module substrate. The reinforcing plate covers the sensor mounting hole. An upper surface of the image sensor chip may be exposed by the module substrate. The reinforcing pattern is adjacent to the sensor mounting hole and extends in at least one direction.Type: GrantFiled: September 12, 2018Date of Patent: August 18, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-Hwang Kim, Hyo-Eun Kim, Jong-Bo Shim, Cha-Jea Jo, Sang-Uk Han
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Publication number: 20200194331Abstract: A semiconductor includes a lower structure, an upper structure on the lower structure, and a connection pattern between the lower structure and the upper structure. The connection pattern is configured to electrically connect the lower structure and the upper structure to each other. The lower structure includes a lower base and a first lower chip on the lower base. The first lower chip includes a chip bonding pad, a pad structure, and a heat sink structure. The connection pattern is connected to the upper structure and extends away from the upper structure to be connected to the pad structure. The pad structure has a thickness greater than a thickness of the chip bonding pad. At least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure.Type: ApplicationFiled: September 25, 2019Publication date: June 18, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Hwang KIM, Jong Bo SHIM, Jang Woo LEE, Yung Cheol KONG, Young Hoon HYUN
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Patent number: 10685921Abstract: A semiconductor chip module includes a chip package and a printed circuit board (PCB) to which the chip package is mounted. The chip package includes a substrate, a processor disposed in a central region of the substrate, a plurality of active chips disposed around the processor, a plurality of dummy chips disposed in spaces between the plurality of active chips, and an epoxy resin fixing the plurality of active chips and the plurality of dummy chips to the substrate. Channels of the epoxy resin extend between an uppermost surface of a chip body of each of the dummy chips and the substrate of the chip package to control or mitigate warping of the chip package.Type: GrantFiled: November 23, 2018Date of Patent: June 16, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Young Kun Jee, Ji Hwang Kim, Un Byoung Kang
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Patent number: 10651224Abstract: A semiconductor package includes a first semiconductor chip. A second semiconductor chip is below the first semiconductor chip. A third semiconductor chip is below the second semiconductor chip. The second semiconductor chip includes a first surface in direct contact with the first semiconductor chip, and a second surface facing the third semiconductor chip. A first redistribution pattern is on the second surface of the second semiconductor chip and is electrically connected to the third semiconductor chip. The third semiconductor chip includes a third surface facing the second semiconductor chip. A conductive pad is on the third surface.Type: GrantFiled: August 8, 2018Date of Patent: May 12, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwang Kim, Chajea Jo, Hyoeun Kim, Jongbo Shim, Sang-uk Han
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Publication number: 20200118972Abstract: A semiconductor package includes a first package substrate, a first semiconductor chip on the first package substrate, a plurality of first chip connection units to connect the first package substrate to the first semiconductor chip, an interposer on the first semiconductor chip, the interposer having a width greater than a width of the first semiconductor chip in a direction parallel to an upper surface of the first package substrate, and an upper filling layer including a center portion and an outer portion, the center portion being between the first semiconductor chip and the interposer, and the outer portion surrounding the center portion and having a thickness greater than a thickness of the center portion in a direction perpendicular to the upper surface of the first package substrate.Type: ApplicationFiled: May 9, 2019Publication date: April 16, 2020Inventors: Jang-woo LEE, Un-byoung KANG, Ji-hwang KIM, Jong-bo SHIM, Young-kun JEE
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Publication number: 20200075561Abstract: A semiconductor package includes a first substrate, a first semiconductor chip mounted on the first substrate, an interposer substrate and a chip package stacked on the first semiconductor chip, and a first molding layer encapsulating the first semiconductor chip and the chip package. The chip package includes a second semiconductor chip on the interposer substrate. The interposer substrate has a base layer consisting of silicon, a conductive pattern on a top surface of the base layer, and a through-electrode extending through the base layer and connected to the conductive pattern.Type: ApplicationFiled: March 11, 2019Publication date: March 5, 2020Inventors: JI HWANG KIM, JONGBO SHIM, WON IL LEE, JANGWOO LEE, YOUNG KUN JEE
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Publication number: 20200051954Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.Type: ApplicationFiled: March 11, 2019Publication date: February 13, 2020Inventors: HYOEUN KIM, JI HWANG KIM, JISUN YANG, SEUNGHOON YEON, CHAJEA JO, SANG-UK HAN