Abstract: Provided is a method of improving skin condition by applying to the skin of a subject a cosmetic composition comprising black yeast-derived exosomes as an active ingredient and thereby improving the skin condition, particularly skin elasticity improvement, skin wrinkle reduction, skin texture improvement, skin tone improvement, skin brightness improvement, skin regeneration, skin moisturization, and/or whitening.

Abstract: Embodiments provide a display device that includes a substrate, a transistor disposed on the substrate, and a light emitting device that is electrically connected to the transistor. The light emitting device includes a first electrode that is electrically connected to the transistor, a second electrode disposed on the first electrode, a light emitting layer disposed between the first electrode and the second electrode, a hole transport layer disposed between the first electrode and the light emitting layer, and an electron blocking layer disposed between the hole transport layer and the light emitting layer. Mobility of the hole transport layer is equal to or less than about 2.0*10?3 cm2/(Vs), and a real part of impedance of the light emitting device is equal to or less than about 100?, in a frequency range of about 105 Hz to about 106 Hz.

Abstract: A glass stress test method includes breaking a glass, analyzing a shape of a crack of a broken portion of the glass in a plan view, finding a breakage origin of the glass based on the shape of the crack in the plan view, analyzing a cross-section of the breakage origin, and calculating a stress of the glass based on a cross-sectional analysis result of the breakage origin. The stress of the glass is calculated as a value proportional to a floor constant defined by a condition of a floor surface disposed when the glass is broken.

Abstract: A buffer unit for temporarily storing a substrate includes a housing having a space for storing a substrate therein, one or more slots disposed within the housing for placing a substrate thereon, and a holding unit disposed at a bottom portion of the housing, having a flat and non-inclined top surface, and comprising a built-in wireless charging module. A substrate type sensor is stored at the holding unit.

Abstract: The present specification relates to a conductive structure body, a method for manufacturing the same, and an electrode and an electronic device including the conductive structure body.

Abstract: Provided are a fluorinated compound for patterning a metal or an electrode (cathode), an organic electronic element using the same, and an electronic device thereof, wherein a fine pattern of the electrode is formed by using the fluorinated compound as a material for patterning a metal or an electrode (cathode), without using a shadow mask, and it is possible to more easily apply UDC since it is easy to manufacture a transparent display having high light transmittance.

Abstract: Provided are a fluorinated compound for patterning a metal or an electrode (cathode), an organic electronic element using the same, and an electronic device thereof, wherein a fine pattern of the electrode is formed by using the fluorinated compound as a material for patterning a metal or an electrode (cathode), without using a shadow mask, and it is possible to more easily apply UDC since it is easy to manufacture a transparent display having high light transmittance.

Abstract: Provided are a fluorinated compound for patterning a metal or an electrode (cathode), an organic electronic element using the same, and an electronic device thereof, wherein a fine pattern of the electrode is formed by using the fluorinated compound as a material for patterning a metal or an electrode (cathode), without using a shadow mask, and it is possible to more easily apply UDC since it is easy to manufacture a transparent display having high light transmittance.

Abstract: Provided are a fluorinated compound for patterning a metal or an electrode (cathode), an organic electronic element using the same, and an electronic device thereof, wherein a fine pattern of the electrode is formed by using the fluorinated compound as a material for patterning a metal or an electrode (cathode), without using a shadow mask, and it is possible to more easily apply UDC since it is easy to manufacture a transparent display having high light transmittance.

Abstract: The present invention relates to a composition comprising plant extracts. The composition according to the present invention has a skin whitening effect by reducing the total amount of melanin and tyrosinase activity in melanocytes of the skin, promotes skin regeneration and increases skin elasticity or reduces skin wrinkles by promoting collagen synthesis and inhibiting collagenase activity in fibroblasts of the skin, has an anti-inflammatory effect or a skin soothing effect by inhibiting NO generation, increases the amount of moisture in the skin and has a moisturizing effect by promoting generation of hyaluronic acid in fibroblasts, and has an antioxidant effect by scavenging free radicals. In addition, since the composition of the present invention exhibits a broad antibacterial effect against various bacteria, the composition may be used as a cosmetic composition, a pharmaceutical composition, a skin external preparation, or a food composition.

Abstract: The present invention relates to a cosmetic composition comprising a eutectic mixture containing: an amino acid, an alpha-hydroxy acid, and water; or two types of amino acids. The cosmetic comprises either an amino acid and an alpha-hydroxy acid or two types of amino acids in the form of a eutectic mixture. Thus, a cosmetic composition with excellent skin penetration effect even under weakly acidic or neutral pH conditions, which causes less irritation, can be provided, wherein the cosmetic composition provides excellent keratin exfoliation, reduces the number of pores, enhances skin elasticity, and promotes skin regeneration while having excellent low-temperature stability.

Abstract: A semiconductor device includes a memory string coupled between a source line and a bit line and including a plurality of memory cells, a plurality of word lines, a peripheral circuit configured to apply a program voltage to a word line, apply a first pass voltage to a word line coupled to a first memory cell adjacent to the selected memory cell, and apply a second pass voltage to a second memory cell adjacent to the selected memory cell, and control logic configured to control the peripheral circuit so that the first pass voltage has a higher voltage level than the second pass voltage when a program target level of the selected memory cell is lower than a first threshold value, and the first pass voltage has a lower voltage level than the second pass voltage when the program target level is higher than a second threshold value.

Abstract: A semiconductor memory apparatus includes a memory cell array, a peripheral circuit, and control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a pre-program operation on first memory cells to be programmed to an upper programmed state among the selected memory cells and perform a normal program operation on the selected memory cells after the pre-program operation.

Abstract: A semiconductor device includes a memory string that includes a plurality of memory cells and is coupled between a source line and a bit line. A method for operating the semiconductor device may include: boosting a first channel region in a channel region of the memory string, wherein the channel region includes the first channel region at one side of the selected memory cell and a second channel region at the other side of the selected memory cell; applying a pre-program bias to a gate electrode of the selected memory cell, to inject electrons into a space region of the selected memory cell; and applying a program bias to the gate electrode.

Abstract: A memory device according to an embodiment includes a memory cell block including a plurality of pages with each page corresponding to a word line of a plurality of word lines, a peripheral circuit configured to perform a program operation on the plurality of pages, and control logic configured to control the peripheral circuit to perform the program operation. The control logic changes and sets a bit line voltage applied to bit lines of the memory cell block during a program verify operation of the program operation according to a program order of each of the plurality of pages.

Abstract: Provided herein may be a semiconductor device and a method of operating a semiconductor device. The method may include: performing a first program operation on a selected memory cell using a first program pulse, a first bit line voltage, a first pre-verify voltage, and a first main verify voltage, with a first level difference between the first pre-verify voltage and the first main verify voltage; and performing a second program operation on the selected memory cell using a second program pulse, a second bit line voltage, a second pre-verify voltage, and a second main verify voltage, with a second level difference between the second pre-verify voltage and the second main verify voltage. The second level difference may be less than the first level difference, and the second bit line voltage may have a level higher than a level of the first bit line voltage.

Abstract: A semiconductor device includes a memory string coupled between a source line and a bit line and including a plurality of memory cells, a plurality of word lines, a peripheral circuit configured to apply a program voltage to a word line, apply a first pass voltage to a word line coupled to a first memory cell adjacent to the selected memory cell, and apply a second pass voltage to a second memory cell adjacent to the selected memory cell, and control logic configured to control the peripheral circuit so that the first pass voltage has a higher voltage level than the second pass voltage when a program target level of the selected memory cell is lower than a first threshold value, and the first pass voltage has a lower voltage level than the second pass voltage when the program target level is higher than a second threshold value.

Abstract: A semiconductor memory apparatus includes a memory cell array, a peripheral circuit, and control logic. The memory cell array may include a plurality of memory cells. The peripheral circuit performs a program operation on selected memory cells among the plurality of memory cells. The control logic controls an operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a pre-program operation on first memory cells to be programmed to an upper programmed state among the selected memory cells and perform a normal program operation on the selected memory cells after the pre-program operation.

Abstract: A semiconductor device includes a memory string coupled between a source line and a bit line and including a plurality of memory cells, a plurality of word lines, a peripheral circuit configured to apply a program voltage to a word line, apply a first pass voltage to a word line coupled to a first memory cell adjacent to the selected memory cell, and apply a second pass voltage to a second memory cell adjacent to the selected memory cell, and control logic configured to control the peripheral circuit so that the first pass voltage has a higher voltage level than the second pass voltage when a program target level of the selected memory cell is lower than a first threshold value, and the first pass voltage has a lower voltage level than the second pass voltage when the program target level is higher than a second threshold value.

Abstract: A memory device according to an embodiment includes a memory cell block including a plurality of pages with each page corresponding to a word line of a plurality of word lines, a peripheral circuit configured to perform a program operation on the plurality of pages, and control logic configured to control the peripheral circuit to perform the program operation. The control logic changes and sets a bit line voltage applied to bit lines of the memory cell block during a program verify operation of the program operation according to a program order of each of the plurality of pages.