Patents by Inventor Ji-Jan Chen

Ji-Jan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200304133
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Inventors: Sandeep Kumar GOEL, Ji-Jan CHEN, Stanley JOHN, Yun-Han LEE, Yen-Hao HUANG
  • Patent number: 10680627
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: June 9, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Publication number: 20190229737
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Sandeep Kumar GOEL, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Patent number: 10256828
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: April 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sandeep Kumar Goel, Ji-Jan Chen, Stanley John, Yun-Han Lee, Yen-Hao Huang
  • Patent number: 10156609
    Abstract: A device includes a fault generation circuit and a first fault injection circuit. The fault generation circuit is configured to generate a fault signal and a plurality of control signals according to a mode signal. The first fault injection circuit is configured to inject a first final fault signal to an under-test device based on the fault signal and the plurality of control signals, in order to verify robustness of the under-test device.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sandeep Kumar Goel, Stanley John, Ji-Jan Chen, Yun-Han Lee
  • Publication number: 20180164369
    Abstract: A device includes a fault generation circuit and a first fault injection circuit. The fault generation circuit is configured to generate a fault signal and a plurality of control signals according to a mode signal. The first fault injection circuit is configured to inject a first final fault signal to an under-test device based on the fault signal and the plurality of control signals, in order to verify robustness of the under-test device.
    Type: Application
    Filed: May 23, 2017
    Publication date: June 14, 2018
    Inventors: Sandeep Kumar GOEL, Stanley JOHN, Ji-Jan CHEN, Yun-Han LEE
  • Publication number: 20180152193
    Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.
    Type: Application
    Filed: September 21, 2017
    Publication date: May 31, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Sandeep Kumar GOEL, Ji-Jan CHEN, Stanley JOHN, Yun-Han LEE, Yen-Hao HUANG
  • Patent number: 9847318
    Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: December 19, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Yu Lin, Chin-Her Chien, Ji-Jan Chen, Jung-Rung Jiang, Wei-Pin Changchien
  • Patent number: 9766286
    Abstract: A method for diagnosing a defect is provided. A first candidate pair comprises a first defect candidate and a second defect candidate. A first pattern is generated to distinguish one or more faults of the first defect candidate from one or more faults of the second defect candidate. The first defect candidate is removed responsive to determining that the first pattern does not detect the first defect candidate and determining that an automatic test equipment (ATE) failure log associates the first pattern with failure. Removing the first candidate pair, as well as additional candidate pairs when possible, promotes diagnosis efficiency by reducing a number of computations required.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: September 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuen-Jong Lee, Cheng-Hung Wu, Wei-Cheng Lien, Hui-Ling Lin, Yen-Ling Liu, Ji-Jan Chen
  • Publication number: 20160163680
    Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes first circuit elements where a first portion of the first circuit elements has a defect. The second layer includes second circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second circuit elements for mitigating the defect.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 9, 2016
    Inventors: Kuan-Yu Lin, Chin-Her Chien, Ji-Jan Chen, Jung-Rung Jiang, Wei-Pin Changchien
  • Patent number: 9310431
    Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ling Liu, Nan-Hsin Tseng, Ji-Jan Chen, Wei-Pin Changchien, Samuel C. Pan
  • Publication number: 20160055631
    Abstract: A method for diagnosing a defect is provided. A first candidate pair comprises a first defect candidate and a second defect candidate. A first pattern is generated to distinguish one or more faults of the first defect candidate from one or more faults of the second defect candidate. The first defect candidate is removed responsive to determining that the first pattern does not detect the first defect candidate and determining that an automatic test equipment (ATE) failure log associates the first pattern with failure. Removing the first candidate pair, as well as additional candidate pairs when possible, promotes diagnosis efficiency by reducing a number of computations required.
    Type: Application
    Filed: August 20, 2014
    Publication date: February 25, 2016
    Inventors: Kuen-Jong Lee, Cheng-Hung Wu, Wei-Cheng Lien, Hui-Ling Lin, Yen-Ling Liu, Ji-Jan Chen
  • Patent number: 9269640
    Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Lin, Jung-Rung Jiang, Chin-Her Chien, Ji-Jan Chen, Wei-Pin Changchien
  • Publication number: 20150115329
    Abstract: Provided is a monolithic stacked integrated circuit (IC). The IC includes a first layer over a substrate and a second layer over the first layer. The first layer includes a first plurality of circuit elements where a first portion of the first plurality of circuit elements has defects. The second layer includes a second plurality of circuit elements. The IC further includes interconnect elements coupling the first portion to a second portion of the second plurality of circuit elements for mitigating the defects.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Lin, Jung-Rung Jiang, Chin-Her Chien, Ji-Jan Chen, Wei-Pin Changchien
  • Patent number: 8863062
    Abstract: Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: October 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Lin Chuang, Ji-Jan Chen, Ching-Fang Chen, Yun-Han Lee
  • Patent number: 8832511
    Abstract: A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ji-Jan Chen, Nan-Hsin Tseng, Chin-Chou Liu
  • Patent number: 8707238
    Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co. Ltd.
    Inventors: Yi-Lin Chuang, Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Sandeep Kumar Goel, Yun-Han Lee, Charles C. C. Liu
  • Publication number: 20140049281
    Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).
    Type: Application
    Filed: August 17, 2012
    Publication date: February 20, 2014
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ling Liu, Nan-Hsin Tseng, Ji-Jan Chen, Wei-Pin Changchien, Samuel C. Pan
  • Patent number: 8614571
    Abstract: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: December 24, 2013
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Saurabh Gupta, Ji-Jan Chen, Chi Wei Hu
  • Publication number: 20130326463
    Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 5, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Lin Chuang, Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Sandeep Kumar Goel, Yun-Han Lee, Charles C.C. Liu