Patents by Inventor Ji-Jan Chen

Ji-Jan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130290914
    Abstract: Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.
    Type: Application
    Filed: July 9, 2012
    Publication date: October 31, 2013
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Lin Chuang, Ji-Jan Chen, Ching-Fang Chen, Yun-Han Lee
  • Publication number: 20130127441
    Abstract: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 23, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Hsin TSENG, Chin-Chou LIU, Saurabh GUPTA, Ji-Jan CHEN, Chi Wei HU
  • Patent number: 8384455
    Abstract: An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: February 26, 2013
    Assignee: Industrial Technology Research Institute
    Inventors: Yu Lee, Nai-Chen Cheng, Ji-Jan Chen, Yuan-Hua Chu, Ching-Yuan Yang
  • Publication number: 20130047049
    Abstract: A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.
    Type: Application
    Filed: August 15, 2011
    Publication date: February 21, 2013
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ji-Jan CHEN, Nan-Hsin Tseng, Chin-Chou Liu
  • Publication number: 20120146693
    Abstract: An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.
    Type: Application
    Filed: May 23, 2011
    Publication date: June 14, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu Lee, Nai-Chen Cheng, Ji-Jan Chen, Yuan-Hua Chu, Ching-Yuan Yang
  • Patent number: 8144756
    Abstract: The present invention relates to a jitter measuring system, comprising: a delay circuit for receiving a clock signal and delaying the clock signal to generate a delay signal; a jitter amplifier for receiving the clock signal and delay signal to generate a first signal and a second signal; and a converter for converting a phase different between the first signal and the second signal into a relevant digital code; wherein the phase difference between the first signal and the second signal is an amplification of jitter.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: March 27, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Yu Lee, Nai-Chen Cheng, Ji-Jan Chen
  • Patent number: 8113412
    Abstract: A method includes electrically grounding a first plurality of metal bumps on a first surface of an interconnection component to a common ground plate. A voltage contrast (VC) image of a second plurality of metal bumps of the interconnection component is generated. Grey levels of the second plurality of metal bumps in the VC image are analyzed to find defect connections between the second plurality of metal bumps and respective ones of the first plurality of metal bumps.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: February 14, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd
    Inventors: Nan-Hsin Tseng, Yun-Han Lee, Chin-Chou Liu, Ji-Jan Chen, Wei-Pin Changchien, Chien-Hui Chen
  • Patent number: 8051394
    Abstract: A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: November 1, 2011
    Assignees: Industrial Technology Research Institute, National Central University
    Inventors: Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen-Ching Wu
  • Publication number: 20100088655
    Abstract: A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.
    Type: Application
    Filed: November 3, 2008
    Publication date: April 8, 2010
    Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL CENTRAL UNIVERSITY
    Inventors: Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen-Ching Wu
  • Publication number: 20090088996
    Abstract: The present invention relates to a jitter measuring system, comprising: a delay circuit for receiving a clock signal and delaying the clock signal to generate a delay signal; a jitter amplifier for receiving the clock signal and delay signal to generate a first signal and a second signal; and a converter for converting a phase different between the first signal and the second signal into a relevant digital code; wherein the phase difference between the first signal and the second signal is an amplification of jitter.
    Type: Application
    Filed: September 19, 2008
    Publication date: April 2, 2009
    Applicant: Industrial Technology Research Institute
    Inventors: Yu Lee, Nai-Chen Cheng, Ji-Jan Chen
  • Publication number: 20080133990
    Abstract: Disclosed is a scan test data compression method and decoding apparatus for multiple-scan-chain designs. The apparatus comprises a on-chip decoder connected to a tester. The decoder includes a decoding buffer configured as a multilayer architecture, a controller, and a switching box for receiving a shift signal or a copy signal. The decoding buffer is used to store decoded test data. While the decoder decodes the encoded data, it transmits control signals to both the decoding buffer and the switching box from the controller, and sends the decoded data to scan chains of a CUT for testing through the decoding buffer. This invention has the advantages of simple encoding method, high compression rate, low power consumption in testing, and without the fault coverage loss.
    Type: Application
    Filed: February 7, 2007
    Publication date: June 5, 2008
    Inventors: Shih-Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen-Ching Wu