Patents by Inventor Ji-Jan Chen
Ji-Jan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140049281Abstract: The present disclosure relates to a diagnosis framework to shorten yield learning cycles of technology node manufacturing processes from the high defect density stage to technology maturity. A plurality of defect under test (DUT) structures are designed to capture potential manufacturing issues associated with defect formation. A test structure is formed by arranging the DUT structures within a DUT carrier unit, which has been yield-hardened though heuristic yield analysis such that a defect density of the DUT carrier unit is essentially zero. Possible outcomes of an application of test patterns and various failure scenarios associated with defects formed within the DUT structures within the DUT carrier unit are simulated and stored in a look-up table (LUT). The LUT may then be referenced to determine a location of a defect within the test structure without the need for iterative analysis to correctly select defect candidates for physical failure analysis (PFA).Type: ApplicationFiled: August 17, 2012Publication date: February 20, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yen-Ling Liu, Nan-Hsin Tseng, Ji-Jan Chen, Wei-Pin Changchien, Samuel C. Pan
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Patent number: 8614571Abstract: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.Type: GrantFiled: November 18, 2011Date of Patent: December 24, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Hsin Tseng, Chin-Chou Liu, Saurabh Gupta, Ji-Jan Chen, Chi Wei Hu
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Publication number: 20130326463Abstract: The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs.Type: ApplicationFiled: May 31, 2012Publication date: December 5, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Lin Chuang, Cheng-Pin Chiu, Ching-Fang Chen, Ji-Jan Chen, Sandeep Kumar Goel, Yun-Han Lee, Charles C.C. Liu
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Publication number: 20130290914Abstract: Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies.Type: ApplicationFiled: July 9, 2012Publication date: October 31, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Lin Chuang, Ji-Jan Chen, Ching-Fang Chen, Yun-Han Lee
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Publication number: 20130127441Abstract: Test points on an integrated circuit chip, especially points subject to IR voltage drop along power supply rails, are coupled to comparators controlled by an automatic test controller, all included on the chip. Each test point can have one or more comparators and one or more reference voltages over a testing range. A change of state at a comparator sets a latch that is read and reset by the on-chip automatic test controller during test intervals. The automatic test controller can coordinate with external automatic test equipment that applies stimulus signals to the chip during testing. The greatest voltage drop during a test interval is determined from the latched output of the switched comparator coupled to the lowest reference voltage. The setting and resetting of the latch can be gated through a selectable delay so as to discriminate for excursions that persist for a longer or shorter time.Type: ApplicationFiled: November 18, 2011Publication date: May 23, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Nan-Hsin TSENG, Chin-Chou LIU, Saurabh GUPTA, Ji-Jan CHEN, Chi Wei HU
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Patent number: 8384455Abstract: An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.Type: GrantFiled: May 23, 2011Date of Patent: February 26, 2013Assignee: Industrial Technology Research InstituteInventors: Yu Lee, Nai-Chen Cheng, Ji-Jan Chen, Yuan-Hua Chu, Ching-Yuan Yang
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Publication number: 20130047049Abstract: A device includes a first die coupled to an interconnect structure of an interposer. The first die includes a first BIST circuit configured to generate and output test signals to the interconnection structure of the interposer. A second die is coupled to the interconnect structure of the interposer and includes a second BIST circuit configured to receive signals from the interconnection structure of the interposer in response to the first BIST circuit transmitting the test signals. The second BIST circuit is configured to compare the signals received from the interconnection structure of the interposer to reference signals generated by the second BIST circuit.Type: ApplicationFiled: August 15, 2011Publication date: February 21, 2013Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ji-Jan CHEN, Nan-Hsin Tseng, Chin-Chou Liu
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Publication number: 20120146693Abstract: An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.Type: ApplicationFiled: May 23, 2011Publication date: June 14, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Yu Lee, Nai-Chen Cheng, Ji-Jan Chen, Yuan-Hua Chu, Ching-Yuan Yang
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Patent number: 8144756Abstract: The present invention relates to a jitter measuring system, comprising: a delay circuit for receiving a clock signal and delaying the clock signal to generate a delay signal; a jitter amplifier for receiving the clock signal and delay signal to generate a first signal and a second signal; and a converter for converting a phase different between the first signal and the second signal into a relevant digital code; wherein the phase difference between the first signal and the second signal is an amplification of jitter.Type: GrantFiled: September 19, 2008Date of Patent: March 27, 2012Assignee: Industrial Technology Research InstituteInventors: Yu Lee, Nai-Chen Cheng, Ji-Jan Chen
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Patent number: 8113412Abstract: A method includes electrically grounding a first plurality of metal bumps on a first surface of an interconnection component to a common ground plate. A voltage contrast (VC) image of a second plurality of metal bumps of the interconnection component is generated. Grey levels of the second plurality of metal bumps in the VC image are analyzed to find defect connections between the second plurality of metal bumps and respective ones of the first plurality of metal bumps.Type: GrantFiled: May 13, 2011Date of Patent: February 14, 2012Assignee: Taiwan Semiconductor Manufacturing Company, LtdInventors: Nan-Hsin Tseng, Yun-Han Lee, Chin-Chou Liu, Ji-Jan Chen, Wei-Pin Changchien, Chien-Hui Chen
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Patent number: 8051394Abstract: A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.Type: GrantFiled: November 3, 2008Date of Patent: November 1, 2011Assignees: Industrial Technology Research Institute, National Central UniversityInventors: Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen-Ching Wu
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Publication number: 20100088655Abstract: A yield evaluating apparatus and a method thereof are provided. The yield evaluating apparatus includes a spatial correlation module. The spatial correlation module receives at least one process-related data and a plurality of circuit layouts and obtains a correlation coefficient between unit elements in the circuit layouts according to the process-related data. The spatial correlation module calculates a spatial correlation between elements in each of the circuit layouts according to the correlation coefficient and selects one of the circuit layouts according to the spatial correlations.Type: ApplicationFiled: November 3, 2008Publication date: April 8, 2010Applicants: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE, NATIONAL CENTRAL UNIVERSITYInventors: Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen-Ching Wu
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Publication number: 20090088996Abstract: The present invention relates to a jitter measuring system, comprising: a delay circuit for receiving a clock signal and delaying the clock signal to generate a delay signal; a jitter amplifier for receiving the clock signal and delay signal to generate a first signal and a second signal; and a converter for converting a phase different between the first signal and the second signal into a relevant digital code; wherein the phase difference between the first signal and the second signal is an amplification of jitter.Type: ApplicationFiled: September 19, 2008Publication date: April 2, 2009Applicant: Industrial Technology Research InstituteInventors: Yu Lee, Nai-Chen Cheng, Ji-Jan Chen
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Publication number: 20080133990Abstract: Disclosed is a scan test data compression method and decoding apparatus for multiple-scan-chain designs. The apparatus comprises a on-chip decoder connected to a tester. The decoder includes a decoding buffer configured as a multilayer architecture, a controller, and a switching box for receiving a shift signal or a copy signal. The decoding buffer is used to store decoded test data. While the decoder decodes the encoded data, it transmits control signals to both the decoding buffer and the switching box from the controller, and sends the decoded data to scan chains of a CUT for testing through the decoding buffer. This invention has the advantages of simple encoding method, high compression rate, low power consumption in testing, and without the fault coverage loss.Type: ApplicationFiled: February 7, 2007Publication date: June 5, 2008Inventors: Shih-Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen-Ching Wu