Patents by Inventor Ji-Seok Hong
Ji-Seok Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240413104Abstract: There is provided a semiconductor device with improved product reliability. The semiconductor device includes a substrate, a structure on the substrate and including multilayer metal patterns and multilayer insulating layers, and a pad layer on the structure and including a plurality of bonding pads, wherein a plurality of uppermost patterns at an uppermost layer among the multilayer metal patterns include electrode patterns for transferring signals and alleviation patterns that do not transfer the signals, a first ratio of the alleviation patterns within a first reference shape at a first distance from an edge of the structure is greater than a second ratio of the alleviation patterns within a second reference shape at a second distance from the edge of the structure, and the first distance is greater than the second distance.Type: ApplicationFiled: January 29, 2024Publication date: December 12, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: Sang Cheon PARK, Ji-Seok HONG, Un-Byoung KANG, Ku Young KIM
-
Publication number: 20240332255Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material.Type: ApplicationFiled: June 13, 2024Publication date: October 3, 2024Inventors: HYUEKJAE LEE, JIHOON KIM, JiHwan SUH, SO YOUN LEE, JIHWAN HWANG, TAEHUN KIM, JI-SEOK HONG
-
Patent number: 12040313Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material.Type: GrantFiled: April 12, 2023Date of Patent: July 16, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuekjae Lee, Jihoon Kim, JiHwan Suh, So Youn Lee, Jihwan Hwang, Taehun Kim, Ji-Seok Hong
-
Patent number: 12014977Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same.Type: GrantFiled: May 19, 2023Date of Patent: June 18, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Seok Hong, Dongwoo Kim, Hyunah Kim, Un-Byoung Kang, Chungsun Lee
-
Patent number: 11984425Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.Type: GrantFiled: January 6, 2022Date of Patent: May 14, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-seok Hong, Jin-woo Park
-
Patent number: 11887900Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.Type: GrantFiled: July 6, 2021Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong
-
Patent number: 11887968Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: GrantFiled: October 5, 2021Date of Patent: January 30, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong, Tae Hun Kim, Hyuek Jae Lee
-
Patent number: 11824006Abstract: A semiconductor package includes a first semiconductor chip having a first face and a second face opposite thereto. The first semiconductor chip includes a first wiring layer having a surface that forms the first face. A second semiconductor chip disposed on the first face of the first semiconductor chip includes a second wiring layer directly contacting the first wiring layer. A first mold layer is disposed on one lateral side of the first semiconductor chip and directly contacts the second wiring layer. A first via penetrates the first mold layer. A width of the first wiring layer and the first semiconductor chip in a horizontal direction are substantially the same. A width of the second wiring layer and the second semiconductor chip in the horizontal direction are substantially the same. A height of the first via and the first semiconductor chip in the vertical direction are substantially the same.Type: GrantFiled: October 4, 2021Date of Patent: November 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Byoung-Soo Kwak, Ji-Seok Hong
-
Publication number: 20230290718Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same.Type: ApplicationFiled: May 19, 2023Publication date: September 14, 2023Applicant: Samsung Electronics Co., Ltd.Inventors: JI-SEOK HONG, DONGWOO KIM, HYUNAH KIM, UN-BYOUNG KANG, CHUNGSUN LEE
-
Publication number: 20230253363Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material.Type: ApplicationFiled: April 12, 2023Publication date: August 10, 2023Inventors: HYUEKJAE LEE, JIHOON KIM, JiHwan SUH, SO YOUN LEE, JIHWAN HWANG, TAEHUN KIM, JI-SEOK HONG
-
Patent number: 11688679Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same.Type: GrantFiled: May 19, 2021Date of Patent: June 27, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ji-Seok Hong, Dongwoo Kim, Hyunah Kim, Un-Byoung Kang, Chungsun Lee
-
Patent number: 11658148Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material.Type: GrantFiled: April 21, 2020Date of Patent: May 23, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuekjae Lee, Jihoon Kim, JiHwan Suh, So Youn Lee, Jihwan Hwang, Taehun Kim, Ji-Seok Hong
-
Patent number: 11581257Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.Type: GrantFiled: June 4, 2021Date of Patent: February 14, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae Lee, Ji Hoon Kim, Tae Hun Kim, Ji Seok Hong, Ji Hwan Hwang
-
Patent number: 11329024Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.Type: GrantFiled: July 29, 2020Date of Patent: May 10, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Ji-seok Hong, Jin-woo Park
-
Publication number: 20220139927Abstract: The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film.Type: ApplicationFiled: July 9, 2021Publication date: May 5, 2022Inventors: Ji Hoon CHANG, Jung-Hoon HAN, Ji Seok HONG, Dong-Sik PARK
-
Publication number: 20220130798Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.Type: ApplicationFiled: January 6, 2022Publication date: April 28, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Ji-seok HONG, Jin-woo PARK
-
Publication number: 20220122918Abstract: A semiconductor package includes a first semiconductor chip having a first face and a second face opposite thereto. The first semiconductor chip includes a first wiring layer having a surface that forms the first face. A second semiconductor chip disposed on the first face of the first semiconductor chip includes a second wiring layer directly contacting the first wiring layer. A first mold layer is disposed on one lateral side of the first semiconductor chip and directly contacts the second wiring layer. A first via penetrates the first mold layer. A width of the first wiring layer and the first semiconductor chip in a horizontal direction are substantially the same. A width of the second wiring layer and the second semiconductor chip in the horizontal direction are substantially the same. A height of the first via and the first semiconductor chip in the vertical direction are substantially the same.Type: ApplicationFiled: October 4, 2021Publication date: April 21, 2022Inventors: Byoung-Soo KWAK, Ji-Seok HONG
-
Publication number: 20220068785Abstract: Disclosed are interconnection structures, semiconductor packages including the same, and methods of fabricating the same.Type: ApplicationFiled: May 19, 2021Publication date: March 3, 2022Inventors: JI-SEOK HONG, DONGWOO KIM, HYUNAH KIM, UN-BYOUNG KANG, CHUNGSUN LEE
-
Publication number: 20220028837Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Inventors: Ji Hwan HWANG, Ji Hoon KIM, Ji Seok HONG, Tae Hun KIM, Hyuek Jae LEE
-
Publication number: 20210335680Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.Type: ApplicationFiled: July 6, 2021Publication date: October 28, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyuek Jae LEE, Tae Hun Kim, Ji Hwan Hwang, Ji Hoon Kim, Ji Seok Hong