Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

Abstract: A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.

Abstract: A semiconductor package includes a substrate, a first semiconductor chip on the substrate, a second semiconductor chip on the first semiconductor chip so that the first semiconductor chip is vertically between the second semiconductor chip and the substrate, a first molding layer adjacent to a sidewall of the first semiconductor chip on the substrate, the first molding layer formed of a first molding material, and a second molding layer adjacent to a sidewall of the second semiconductor chip on the substrate so that the first molding layer is vertically between the second molding layer and the substrate. The second molding layer is formed of a second molding material different from the first molding material.

Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.

Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.

Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.

Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.

Abstract: A semiconductor package includes: a lower semiconductor chip including a first semiconductor substrate, which includes a first semiconductor device on an active surface thereof and a protrusion defined by a recess region on an inactive surface thereof opposite to the active surface, a plurality of external connecting pads on a bottom surface of the first semiconductor substrate, and a plurality of through-electrodes electrically connected to the plurality of external connecting pads; and at least one upper semiconductor chip stacked on the protrusion of the lower semiconductor chip and electrically connected to the plurality of through-electrodes, the at least one upper semiconductor chip including a second semiconductor substrate which includes a second semiconductor device on an active surface thereof.

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip and a sealing member. The first semiconductor chip includes a substrate having a first surface and a second surface opposite to the first surface and having an opening that extends in a predetermined depth from the second surface, and a plurality of through electrodes extending in a thickness direction from the first surface, end portions of the through electrodes being exposed through a bottom surface of the opening. The second semiconductor chip is received in the opening and mounted on the bottom surface of the opening. The sealing member covers the second semiconductor chip in the opening.

Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.

Abstract: A semiconductor package of a POP structure includes first and second semiconductor packages, the second directly mounted on the first and containing a plurality of semiconductor chips. Chips in the second package are electrically connected via a through-electrode and the first and second packages are connected through a connection member disposed on the top surface of the first package.

Abstract: Bi-directional camera modules and flip chip bonders including the same are provided. The module includes a circuit board on which an upper sensor and a lower sensor are mounted, an upper lens and a lower lens disposed on the upper sensor and under the lower sensor, respectively, and a housing fixing the upper lens and the lower lens spaced apart from the upper sensor and the lower sensor, respectively. The housing surrounds the circuit board. The housing has a plurality of inlets and an outlet through which air flows, and the housing has an air passage connected from the inlets to the outlet via a space between lower lens and the lower sensor.

Abstract: A method of fabricating a wafer level package includes preparing a wafer including a plurality of first semiconductor chips, mounting a plurality of second semiconductor chips on the wafer, disposing the wafer on a lower mold and disposing an upper mold so as to surround edges of a top surface of the wafer, dispensing a molding member on the wafer, and pressurizing the molding member by using a plunger so as to fabricate a wafer level package in which a top surface of each of the plurality of second semiconductor chips is exposed.

Abstract: A semiconductor package comprises a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a third semiconductor chip on the second semiconductor chip and a fourth semiconductor chip on the third semiconductor chip. A first underfill layer is positioned between the second semiconductor chip and the first semiconductor chip; a second underfill layer is positioned between the third semiconductor chip and the second semiconductor chip, and a third underfill layer is positioned between the fourth semiconductor chip and the third semiconductor chip. In some embodiments, the second underfill layer comprises a material that is different than the first and third underfill layers.

Abstract: Semiconductor packages including a heat spreader and methods of forming the same are provided. The semiconductor packages may include a first semiconductor chip, a second semiconductor chip, and a heat spreader stacked sequentially. The semiconductor packages may also include a thermal interface material (TIM) layer surrounding the second semiconductor chip and directly contacting a sidewall of the second semiconductor chip. An upper surface of the TIM layer may directly contact a lower surface of the heat spreader, and a sidewall of the TIM layer may be substantially coplanar with a sidewall of the heat spreader. In some embodiments, a sidewall of the first semiconductor chip may be substantially coplanar with the sidewall of the TIM layer.

Abstract: A semiconductor device includes a first semiconductor chip at least partially overlapping a second semiconductor chip. The first semiconductor chip is coupled to a substrate and has a first width, and the second semiconductor chip has a second width. The device also includes a heat sink coupled to the second semiconductor chip and having a third width different from at least one of the first width or the second width. A package molding section at least partially overlaps a first area of the heat sink and does not overlap a second area of the heat sink which includes a top surface of the heat sink.