Patents by Inventor Jia Cheng

Jia Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12254215
    Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: March 18, 2025
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Jia-Xing Lin, Nai-Ping Kuo, Shih-Chou Juan, Chien-Hsin Liu, Shunli Cheng
  • Patent number: 12253656
    Abstract: A light-folding element includes an object-side surface, an image-side surface, a reflection surface and a connection surface. The reflection surface is configured to reflect imaging light passing through the object-side surface to the image-side surface. The connection surface is connected to the object-side, image-side and reflection surfaces. The light-folding element has a recessed structure located at the connection surface. The recessed structure is recessed from the connection surface an includes a top end portion, a bottom end portion and a tapered portion located between the top end and bottom end portions. The top end portion is located at an edge of the connection surface. The tapered portion has two tapered edges located on the connection surface. The tapered edges are connected to the top end and bottom end portions. A width of the tapered portion decreases in a direction from the top end portion towards the bottom end portion.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: March 18, 2025
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Min-Chun Liao, Lin An Chang, Ming-Ta Chou, Jyun-Jia Cheng, Cheng-Feng Lin, Ming-Shun Chang
  • Publication number: 20250089403
    Abstract: A transparent display device includes a transparent display panel and a functional film. The transparent display panel includes a transparent substrate and a pixel array. The functional film is disposed on the transparent display panel. The pixel array is located between the functional film and the transparent substrate. A surface of the functional film facing away from the transparent substrate has raised microstructures. At least a portion of each of the raised microstructures extends in a first oblique direction. A size of the least a portion of each of the raised microstructures is gradually decreased along the first oblique direction. The first oblique direction forms an acute angle ? with a normal direction of the transparent substrate.
    Type: Application
    Filed: November 30, 2023
    Publication date: March 13, 2025
    Applicant: AUO Corporation
    Inventors: YuTang Tsai, Wang-Shuo Kao, Jia Hao Hsu, Kun-Cheng Tien, Jia-Long Wu
  • Publication number: 20250084101
    Abstract: The present invention relates to a compound represented by general formula (I) or a stereoisomer, deuterated compound, solvate, prodrug, metabolite, pharmaceutically acceptable salt or eutectic crystal thereof, and an intermediate thereof, and use thereof in IRAK4-related diseases such as an autoimmune disease, an inflammatory disease or cancer.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 13, 2025
    Applicant: XIZANG HAISCO PHARMACEUTICAL CO., LTD.
    Inventors: Chen ZHANG, Yuting LIAO, Chenfei ZHAO, Yan YU, Pingming TANG, Junjie MA, Xiaogang CHEN, Shuai YUAN, Xinfan CHENG, Fei YE, Yao LI, Jia NI, Pangke YAN
  • Patent number: 12243918
    Abstract: A device includes a gate structure, first and second gate spacers, source/drain regions, a refill metal structure, and a first dielectric liner. The gate structure is on a substrate. The first and second gate spacers are on opposite sides of the gate structure, respectively. The source/drain regions are spaced part from the gate structure at least in part by the first and second gate spacers. The refill metal structure is on the gate structure and between the first and second gate spacers. The first di electric liner is atop the gate structure. The first dielectric liner interposes the refill metal structure and the first gate spacer.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Hsiang Wu, Jia-Chuan You, Chia-Hao Chang, Kuo-Cheng Chiang, Chih-Hao Wang
  • Publication number: 20250069881
    Abstract: Embodiments are directed to a method for minimizing electrostatic charges in a semiconductor substrate. The method includes depositing photoresist on a semiconductor substrate to form a photoresist layer on the semiconductor substrate. The photoresist layer is exposed to radiation. The photoresist layer is developed using a developer solution. The semiconductor substrate is cleaned with a first cleaning liquid to wash the developer solution from the photoresist layer. A tetramethylammonium hydroxide (TMAH) solution is applied to the semiconductor substrate to reduce charges accumulated in the semiconductor substrate.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Lin CHANG, Chih-Chien WANG, Chihy-Yuan CHENG, Sz-Fan CHEN, Chien-Hung LIN, Chun-Chang CHEN, Ching-Sen KUO, Feng-Jia SHIU
  • Publication number: 20250072050
    Abstract: An integrated circuit includes a transistor having a plurality of stacked channels each extending between the source/drain regions of the transistor. The transistor also includes a hard mask nanostructure above the highest channel and extending between the source/drain regions of the transistor. A gate dielectric and gate metals wrap around the channels and the hard mask nanostructure.
    Type: Application
    Filed: January 4, 2024
    Publication date: February 27, 2025
    Inventors: Chung-Wei HSU, Lung-Kun CHU, Jia-Ni YU, Chun-Fu LU, Shih-Hao LAI, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12237372
    Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Jia-Ni Yu, Chung-Wei Hsu, Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Mao-Lin Huang
  • Patent number: 12237418
    Abstract: A semiconductor device includes a semiconductor layer. A gate structure is disposed over the semiconductor layer. A spacer is disposed on a sidewall of the gate structure. A height of the spacer is greater than a height of the gate structure. A liner is disposed on the gate structure and on the spacer. The spacer and the liner have different material compositions.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Chih-Hao Wang, Kuo-Cheng Chiang, Wei-Hao Wu, Zhi-Chang Lin, Jia-Ni Yu, Yu-Ming Lin, Chung-Wei Hsu
  • Patent number: 12237396
    Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jia-Ni Yu, Kuo-Cheng Chiang, Lung-Kun Chu, Chung-Wei Hsu, Chih-Hao Wang, Mao-Lin Huang
  • Patent number: 12237373
    Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.
    Type: Grant
    Filed: April 3, 2023
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Lung-Kun Chu, Jia-Ni Yu, Chung-Wei Hsu, Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Mao-Lin Huang
  • Publication number: 20250063792
    Abstract: Gate isolation processes (e.g., gate-to-source/drain contact isolation) are described herein. An exemplary contact gate isolation process may include recessing (e.g., by etching) sidewall portions of a high-k gate dielectric and gate spacers of a gate structure to form a contact gate isolation (CGI) opening that exposes sidewalls of a gate electrode of the gate structure, forming a gate isolation liner along the sidewalls of the gate electrode that partially fills the CGI opening, and forming a gate isolation layer over the gate isolation liner that fills a remainder of the CGI opening. A dielectric constant of the gate isolation liner is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer is less than a dielectric constant of the high-k gate dielectric. A dielectric constant of the gate isolation layer may be less than a dielectric constant of the gate isolation layer.
    Type: Application
    Filed: December 1, 2023
    Publication date: February 20, 2025
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Chu-Yuan HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250063879
    Abstract: A transparent display apparatus includes a transparent substrate, a first pixel array and a light leakage suppression element. The transparent substrate has display areas and transparent areas. The first pixel array is disposed on the transparent substrate and includes first pixels and first openings. Each of the first pixel overlaps with a corresponding display area. Each of the first opening overlaps with a corresponding transparent area. The light leakage suppression element includes light blocking structures spaced apart from each other. The first pixels are disposed on a first side of the transparent substrate. At least a portion of each of the light blocking structures of the light leakage suppression element is disposed on a second side of the transparent substrate.
    Type: Application
    Filed: December 8, 2023
    Publication date: February 20, 2025
    Applicant: AUO Corporation
    Inventors: YuTang Tsai, Wang-Shuo Kao, Jia Hao Hsu, Kun-Cheng Tien
  • Publication number: 20250063808
    Abstract: A semiconductor structure includes a first dielectric wall over a substrate, and two metal gate structures disposed at two sides of the first dielectric wall. Each of the metal gate structures includes a plurality of nanosheets stacked over the substrate and separated from each other, a high-k gate dielectric layer covering each of the nanosheets, and a metal layer covering and over the plurality of nanosheets and the high-k gate dielectric layer. The high-k gate dielectric layer of each metal gate structure is disposed between the metal layer of each metal gate structure and the first dielectric wall.
    Type: Application
    Filed: August 17, 2023
    Publication date: February 20, 2025
    Inventors: KUAN-TING PAN, JIA-CHUAN YOU, CHIA-HAO CHANG, KUO-CHENG CHIANG, CHIH-HAO WANG
  • Publication number: 20250056848
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The method includes forming a metal gate stack wrapped around multiple semiconductor nanostructures. The semiconductor nanostructures are beside an epitaxial structure. The method includes forming a dielectric layer over the metal gate stack and the epitaxial structure. The method further includes forming a contact opening in the dielectric layer and forming a protective layer over sidewalls of the contact opening. In addition, the method includes deepening the contact opening so that the contact opening extends into the epitaxial structure after the formation of the protective layer. The method includes forming a conductive contact filling the contact opening.
    Type: Application
    Filed: August 9, 2023
    Publication date: February 13, 2025
    Inventors: Chu-Yuan HSU, Jia-Chuan YOU, Chia-Hao CHANG, Kuo-Cheng CHIANG, I-Han HUANG
  • Publication number: 20250056867
    Abstract: An integrated circuit includes a nanosheet transistor having a plurality of stacked channels, a gate electrode surrounding the stacked channels, a source/drain region, and a source/drain contact. The integrated circuit includes a first dielectric layer between the gate metal and the source/drain contact, a second dielectric layer on the first dielectric layer, and a cap metal on the first gate metal and on a hybrid fin structure. The second dielectric layer is on the hybrid fin structure between the cap metal and the source/drain contact.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Chia-Hao CHANG, Jia-Chuan YOU, Chu-Yuan HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250054765
    Abstract: An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.
    Type: Application
    Filed: October 30, 2024
    Publication date: February 13, 2025
    Inventors: Jia-Chuan YOU, Chia-Hao CHANG, Chu-Yuan HSU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Patent number: 12218372
    Abstract: A neck-mounted power bank is suitable for being hung on a user's neck to supply power to an electronic device. The neck-mounted power bank includes a body, a battery, and a pair of adjustable assemblies. The battery is disposed in the body. The pair of adjustable assemblies are respectively connected to two ends of the body, and define a wearing space with the body. The pair of adjustable assemblies can be rotated relative to the body so as to adjust the size of the wearing space. Each of the pair of adjustable assemblies includes a rotate arm and an angle arm. The rotate arm is rotatably connected to a corresponding end of the body. The angle arm is connected to the rotate arm and has a contact surface. The contact surface is suitable for contacting the user's neck.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: February 4, 2025
    Assignee: HTC Corporation
    Inventors: Jia Shan Wu, Wei-Cheng Liu, Chun-Lung Chu
  • Publication number: 20250040187
    Abstract: Various embodiments of the present disclosure provide a semiconductor device structure. In one embodiment, the semiconductor device structure includes a dielectric wall disposed over a substrate, first and second metal gate structure portions respectively disposed at either side of the dielectric wall. Each first and second metal gate structure portion includes a plurality of semiconductor layers vertically stacked and separated from each other, a high-K (HK) dielectric layer disposed to surround at least three surfaces of each of the semiconductor layers, and a gate electrode layer disposed between two neighboring semiconductor layers. The semiconductor device structure also includes a metal layer disposed on two opposing sidewalls of the dielectric wall.
    Type: Application
    Filed: December 4, 2023
    Publication date: January 30, 2025
    Inventors: Chia-Hao CHANG, Kuan-Ting PAN, Jia-Chuan YOU, Kuo-Cheng CHIANG, Chih-Hao WANG
  • Publication number: 20250036977
    Abstract: An electronic device is configured to execute instructions: compiling a first AI model and second AI model(s) to a first compiled file and second compiled file(s), respectively, wherein the first compiled file comprises a first data set and a first command set, and the second compiled file(s) comprises second data set(s) and second command set(s); generating light version file(s) for the AI model(s), wherein the light version file(s) comprises the second command set(s) and data patch(es); storing the first compiled file and the light version file(s) to a storage device; loading the first compiled file from the storage device to a memory; loading the light version file(s) from the storage device to the memory; generating the second data set(s) according to the first data set and the data patch(es); and executing the second AI model(s) according to the generated second data set(s) and the second command set(s) in the memory.
    Type: Application
    Filed: June 23, 2024
    Publication date: January 30, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chia-Wei Hsu, Yu-Lung Lu, Yen-Ting Chiang, Chih-wei Chen, Yi-Cheng Lu, Jia-Sian Hong, Kuan-Yu Chen, Pei-Kuei Tsung, Hua Wu