Abstract: A memory device and a management method thereof are provided. The memory device includes a controller and at least one memory channel. The memory channel includes at least one memory chip. The at least one memory chip is commonly coupled to the controller through an interrupt signal wire. The at least one memory chip generates at least one local interrupt signal and performs a logic operation on the at least one local interrupt signal to generate a common interrupt signal. The interrupt signal wire is configured to transmit the common interrupt signal to the controller.

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

Abstract: A semiconductor device according to the present disclosure includes a source feature and a drain feature, a plurality of semiconductor nanostructures extending between the source feature and the drain feature, a gate structure wrapping around each of the plurality of semiconductor nanostructures, a bottom dielectric layer over the gate structure and the drain feature, a backside power rail disposed over the bottom dielectric layer, and a backside source contact disposed between the source feature and the backside power rail. The backside source contact extends through the bottom dielectric layer.

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first channel structure configured to transport charge carriers within a first transistor device and a first gate electrode layer wrapping around the first channel structure. A second channel structure is configured to transport charge carriers within a second transistor device. A second gate electrode layer wraps around the second channel structure. The second gate electrode layer continuously extends from around the second channel structure to cover the first gate electrode layer. A third channel structure is configured to transport charge carriers within a third transistor device. A third gate electrode layer wraps around the third channel structure. The third gate electrode layer continuously extends from around the third channel structure to cover the second gate electrode layer.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region of a substrate, respectively, and sequentially depositing a gate dielectric layer, an n-type work function metal layer, and a cap layer surrounding each of the first and second channel nanostructures. The cap layer merges in first spaces between adjacent first channel nanostructures and merges in second spaces between adjacent second channel nanostructures. The method further includes selectively removing the cap layer and the n-type work function metal layer in the p-type device region, and depositing a p-type work function metal layer over the cap layer in the n-type device region and the gate dielectric layer in the p-type device region. The p-type work function metal layer merges in the second spaces.

Abstract: A data writing method, a memory storage device, and a memory control circuit unit are provided. The method includes: receiving a write command from a host system, and the write command including first data; checking a status of a first physical programming unit in a first physical erasing unit; in response to the status of the first physical programming unit being a first status, sending a first command sequence to a rewritable non-volatile memory module, and the first command sequence being configured to instruct the rewritable non-volatile memory module to store at least part of the first data to the first physical programming unit.

Abstract: A light-folding element includes an object-side surface, an image-side surface, a reflection surface and a connection surface. The reflection surface is configured to reflect imaging light passing through the object-side surface to the image-side surface. The connection surface is connected to the object-side, image-side and reflection surfaces. The light-folding element has a recessed structure located at the connection surface. The recessed structure is recessed from the connection surface an includes a top end portion, a bottom end portion and a tapered portion located between the top end and bottom end portions. The top end portion is located at an edge of the connection surface. The tapered portion has two tapered edges located on the connection surface. The tapered edges are connected to the top end and bottom end portions. A width of the tapered portion decreases in a direction from the top end portion towards the bottom end portion.

Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first channel structure and a second channel structure over a substrate. The semiconductor device structure also includes a first gate stack over the first channel structure, and the first gate stack has a first width. The semiconductor device structure further includes a second gate stack over the second channel structure. The second gate stack has a protruding portion extending away from the second channel structures. The protruding portion of the second gate stack has a second width, and half of the first width is greater than the second width.

Abstract: This disclosure provides a lens assembly that has an optical path and includes a lens element and a light-blocking membrane layer. The lens element has an optical portion, and the optical path passes through the optical portion. The light-blocking membrane layer is coated on the lens element and adjacent to the optical portion. The light-blocking membrane layer has a distal side and a proximal side that is located closer to the optical portion than the distal side. The proximal side includes two extension structures and a recessed structure. Each of the extension structures extends along a direction away from the distal side, and the extension structures are not overlapped with each other in a direction in parallel with the optical path. The recessed structure is connected to the extension structures and recessed along a direction towards the distal side.

Abstract: An imaging lens assembly has an optical axis, and includes a plastic carrier element and an imaging lens element set. The plastic carrier element includes an object-side surface, an image-side surface, an outer surface and an inner surface. The object-side surface includes an object-side opening. The image-side surface includes an image-side opening. The inner surface is connected to the object-side opening and the image-side opening. The imaging lens element set is disposed in the plastic carrier element, and includes at least three lens elements, each of at least two adjacent lens elements of the lens elements includes a first axial assembling structure, the first axial assembling structures are corresponding to and connected to each other. A solid medium interval is maintained between the adjacent lens elements and the inner surface. The solid medium interval is directly contacted with the adjacent lens elements and the inner surface.

Abstract: A semiconductor device according to the present disclosure includes a first gate structure and a second gate structure aligned along a direction, a first metal layer disposed over the first gate structure, a second metal layer disposed over the second gate structure, and a gate isolation structure extending between the first gate structure and the second gate structure as well as between the first metal layer and the second metal layer.

Abstract: A polymer and a light-emitting device employing the same are provided. The polymer includes a first repeat unit with a structure represented by Formula (I): wherein the definitions of R1, R2, A1, A2, A3, and Z1 and n are as defined in the specification. At least one of A1, A2, and A3 is not hydrogen.

Abstract: The present invention relates to an organic compound, an organic electroluminescent material, and an organic electroluminescent element. The structural formula of the compound is shown in formula (I). When the organic compound of the present invention is used for preparing an organic electroluminescent element, the electron mobility, thermal stability, and luminescent characteristics are excellent; and the organic compound can be applied to an organic layer of the organic electroluminescent element. The organic compound of the present invention has a relatively good film-forming property; and when same is applied to an electron transport layer and an electron transport auxiliary layer, an organic electroluminescent element, which has a lower driving voltage, a higher light emission efficiency, and a longer service life than existing electron transport materials, can be manufactured, and thus, a full-color display panel with having improved performance and a prolonged service life can be manufactured.

Abstract: A transparent display panel with driving electrode regions, circuit wiring regions, and optically transparent regions is provided. The driving electrode regions are arranged into an array in a first direction and a second direction. An average light transmittance of the circuit wiring regions is less than ten percent, and an average light transmittance of the optically transparent regions is greater than that of the driving electrode regions and the circuit wiring regions. The first direction intersects the second direction. The circuit wiring regions connect the driving electrode regions at intervals, such that each optically transparent region spans among part of the driving electrode regions. The transparent display panel includes first signal lines and second signal lines extending along the circuit wiring regions, and each circuit wiring region is provided with at least one of the first signal lines and at least one of the second signal lines.

Abstract: A dual power switching system includes a first STS, a second STS, an inductive device, and a controller. The first STS is electrically coupled to a main power source, and the second STS is electrically coupled to a backup power source. When detecting that the main power source is abnormal, the controller detects a residual magnetic flux of the inductive device and calculates a magnetic flux difference between the predicted magnetic flux and the residual magnetic flux. When determining that an absolute value of the magnetic flux difference is less than or equal to a magnetic flux deviation value, the controller determines whether the output power meets a forced commutation condition. When determining that the output power meets the forced commutation condition, the controller turns on the second STS so that the first STS is forcibly turned off by the backup power source through the second STS.

Abstract: A shiftable image sensor module includes an image sensor and a shiftable circuit element. The shiftable circuit element includes a movable portion, a fixed portion, an elastic connecting portion and a conducting wire portion. The image sensor is disposed on the movable portion. The fixed portion is disposed around the movable portion. The elastic connecting portion is connected to the movable portion and the fixed portion. The conducting wire portion includes a plurality of conducting wire units, and each of the conducting wire units is electrically connected from the fixed portion to the image sensor. Each of the conducting wire units includes at least one conductor line, and the conductor line includes an air insulation layer located on an outer surface of the conductor line.

Abstract: In at least one embodiment, under the control of a robotic control system, a gripper on a robot is positioned to grasp a 3-dimensional object. In at least one embodiment, the relative position of the object and the gripper is determined, at least in part, by using a camera mounted on the gripper.

Abstract: The present disclosure provides Low Temperature NOx-Absorber (LT-NA) catalyst compositions, catalyst articles, and an emission treatment system for treating an exhaust gas, each including the LT-NA catalyst compositions. Further provided are methods for reducing a NOx level in an exhaust gas stream using the LT-NA catalyst articles. In particular, the LT-NA catalyst compositions include a first zeolite, a first palladium component, and a plurality of platinum nanoparticles. The LT-NA catalyst compositions exhibit enhanced regeneration efficiency with respect to NOx adsorption capacity, even after hydrothermal aging.

Abstract: A light-folding element includes an object-side surface, an image-side surface, a reflection surface and a connection surface. The reflection surface is configured to reflect imaging light passing through the object-side surface to the image-side surface. The connection surface is connected to the object-side, image-side and reflection surfaces. The light-folding element has a recessed structure located at the connection surface. The recessed structure is recessed from the connection surface an includes a top end portion, a bottom end portion and a tapered portion located between the top end and bottom end portions. The top end portion is located at an edge of the connection surface. The tapered portion has two tapered edges located on the connection surface. The tapered edges are connected to the top end and bottom end portions. A width of the tapered portion decreases in a direction from the top end portion towards the bottom end portion.