Abstract: An operational transconductance amplifier for connection with multiple input voltage sources includes a resistance simulation unit, two current cancellation units, a first differential output unit, two current division units, and a second differential output unit. The resistance simulation unit is to simulate resistance. The two current cancellation units are to receive and convert the voltage of the input voltage sources into two first currents. The two first currents flow to two first output ends of the first differential output unit, respectively. The two current division units are to receive and convert the voltage of the input voltage sources into two second currents. The two second currents flow to two second output ends of the two second differential output units, respectively, and include the same potential as the two first currents.

Abstract: A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

Abstract: An operational transconductance amplifier for connection with multiple input voltage sources includes a resistance simulation unit, two current cancellation units, a first differential output unit, two current division units, and a second differential output unit. The resistance simulation unit is to simulate resistance. The two current cancellation units are to receive and convert the voltage of the input voltage sources into two first currents. The two first currents flow to two first output ends of the first differential output unit, respectively. The two current division units are to receive and convert the voltage of the input voltage sources into two second currents. The two second currents flow to two second output ends of the two second differential output units, respectively, and include the same potential as the two first currents.

Abstract: In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.

Abstract: An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including a first region of a first doping type, a second region of the first doping type spaced from the first region, a drift region of the first doping type positioned between the first region and the second region, and regions of the opposite doping type. A mask covering both the drift region and the regions of the opposite doping type is formed. Then, a source/drain ion implantation is performed into the first region and the second region. The mask prevents the drift region and the regions of the opposite doping type from receiving the source/drain ion implantation.

Abstract: An approach for providing sub-circuit models with corner instances for VLSI designs is disclosed. Embodiments include: determining a circuit design that includes a plurality of sub-circuit models having a plurality of characteristics; and associating, by a processor, a sub-circuit model of the plurality of sub-circuit models with a corner instance value, and another sub-circuit model of the plurality of sub-circuit models with another corner instance value. Other embodiments include analyzing, by the processor, the circuit design according to the corner instance value and the other corner instance value.

Abstract: In an embodiment, a method performed by one or more computing devices comprises storing, for one or more marketplace associated applications, interaction information that identifies, for each particular application of said one or more marketplace associated applications, a list of devices that interacted with an instance of the particular application; receiving, from a requesting device, a request for a list of offer eligible applications; determining, based on said interaction information, a set of applications associated with the requesting device; based on said determination of the set of applications associated with the requesting device, sending a list of one or more selected eligible applications to the requesting device.

Abstract: A method for modeling a transistor includes providing a transistor model having at least a source node, a drain node, and a gate node, simulating operation of a device using the transistor model in a computing apparatus, and generating an offset voltage at the gate node depending on a magnitude of a current passing through the device.

Abstract: The present invention provides a thin film solar cell, which comprises: a substrate; a first electrode disposed on the substrate; a barrier layer disposed on the first electrode, wherein the material of the barrier layer is a conductive material; an ohmic contacting layer disposed on the barrier layer; an absorption layer disposed on the ohmic contacting layer; a buffer layer disposed on the absorption layer; a transparent conductive layer disposed on the buffer layer; and a second electrode disposed on the transparent conductive layer. In addition, the present invention also provides a method for manufacturing the aforementioned thin film solar cell.

Abstract: Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material, such as Ge or a semiconductor compound, is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location.

Abstract: Single-crystalline growth is realized using a liquid-phase crystallization approach involving the inhibition of defects typically associated with liquid-phase crystalline growth of lattice mismatched materials. According to one example embodiment, a semiconductor device structure includes a substantially single-crystal region. A liquid-phase material, such as Ge or a semiconductor compound, is crystallized to form the single-crystal region using an approach involving defect inhibition for the promotion of single-crystalline growth. In some instances, this defect inhibition involves the reduction and/or elimination of defects using a relatively small physical opening via which a crystalline growth front propagates. In other instances, this defect inhibition involves causing a change in crystallization front direction relative to a crystallization seed location.

Abstract: A pouch has two sheet walls bonded to each other at peripheral edges thereof. A storage chamber is formed in between the sheet walls. The storage chamber has a main chamber and a sub-chamber. The sub-chamber connects to the main chamber and has a smaller size than the main chamber. A bonding potion is defined at an area on the pouch beside the sub-chamber. The sheet walls are fastening to each other at the bonding potion. A guiding line disposes at the bonding potion extending from the end thereof to the sub-chamber. The guiding line divides the bonding potion into a first segment and a second segment. A gap is disposed at the edge of the pouch at the distal end of the guiding line, whereby user can exert the first and the second segments of the bonding potion to tear them apart along the guiding line.

Abstract: Isolated nucleic acid molecules comprising polynucleotide having sequences that encode human and Drosophila PAR-1 kinases. Also provided are proteins and polypeptides encoded by the nucleic acid molecules, methods of modulating PAR-1 expression and function, and methods of modulating the Wnt signaling pathway.