Abstract: A manufacturing method for a LED is disclosed. The method includes: providing a substrate with an upper surface; preparing a plurality of LEDs on the upper surface; wherein the upper surface is divided into a plurality of zones, the plurality of LEDs composes a plurality of LED groups, and each of the LED group is disposed in one of the plurality of zones; preparing a testing circuit to electrically connecting the plurality of LEDs in one of the plurality of LED groups; testing the plurality of LEDs in the one of the plurality of LED groups by the testing circuit to obtain photoelectrical characteristics of the plurality of LEDs in the one of the plurality of LED groups; and presenting the photoelectric characteristics in an image.

Abstract: Various aspects of the disclosure relate to identifying and disabling dormant service accounts. An account management system automatically analyzes service account activity records to determine whether each service account defined for an enterprise network is in use. Automated monitoring applications may be used for identifying and authenticating events and/or authentications of service accounts across an enterprise network. When particular service accounts are identified as being potentially dormant, based on an identified date of last use meeting a threshold condition, the associated service accounts are flagged as being dormant. Setting an account as being dormant triggers solicitation of feedback confirming the dormant setting, which causes disablement of the service account. The account management system triggers decommissioning of the dormant service accounts upon expiration of a disablement threshold.

Abstract: A cooling device for a rotor assembly of a gas turbine engine includes an airflow nozzle configured to be installed at a cooling location of the rotor assembly. The airflow nozzle extends entirely around a circumference of the rotor assembly and includes a plurality of airflow inlets and a nozzle outlet to direct an airflow toward the cooling location. An airflow source is operably connected to the plurality of airflow inlets.

Abstract: A manufacturing method for a LED is disclosed. The method includes: providing a substrate with an upper surface; preparing a plurality of LEDs on the upper surface; wherein the upper surface is divided into a plurality of zones, the plurality of LEDs composes a plurality of LED groups, and each of the LED group is disposed in one of the plurality of zones; preparing a testing circuit to electrically connecting the plurality of LEDs in one of the plurality of LED groups; testing the plurality of LEDs in the one of the plurality of LED groups by the testing circuit to obtain photoelectrical characteristics of the plurality of LEDs in the one of the plurality of LED groups; and presenting the photoelectric characteristics in an image.

Abstract: A method of biasing a substrate includes electrically connecting a silicide structure to a bias voltage supply. The method further includes conducting a bias voltage received by the silicide structure to a silicide extension extending from a main body of the silicide structure, wherein the silicide extension extends between adjacent gate structures of a plurality of first gate structures. The method further includes transferring the bias voltage from the silicide extension into a doped region of a substrate below the adjacent gate structures of the plurality of first gate structures.

Abstract: A method for testing electronic products implemented in an electronic device includes selecting a serial port connected with a slave device in serial communication with a product under test. An activation instruction is transmitted to the slave device, and the electronic product is started through the slave device. Data stored in at least one register of the electronic product and a state of the electronic product is obtained and a capacitance of at least one capacitor in the electronic product is measured. When the electronic product is found to be in an abnormal state, determining a cause of abnormality according to data of the electronic product and the capacitance of the at least one capacitor.

Abstract: A cooling device for a rotor assembly of a gas turbine engine includes an airflow nozzle configured to be installed at a cooling location of the rotor assembly. The airflow nozzle extends entirely around a circumference of the rotor assembly and includes a plurality of airflow inlets and a nozzle outlet to direct an airflow toward the cooling location. An airflow source is operably connected to the plurality of airflow inlets.

Abstract: A manufacturing method for an LED includes: providing a substrate having an upper surface divided into a plurality of zones; a LED group formed on each of the zones and wherein: a plurality of the LED groups includes a first LED group; and the LEDs of the first LED group include a defective LED; forming a testing circuit on the substrate to electrically connect the LEDs; testing the first LED group by the testing circuit; recording a position of the defective LED; providing a carrier; and performing one of the following steps by the position of the defective LED: removing the defective LED from the substrate and then transferring the other LEDs in the first LED group to the carrier; transferring the other LEDs other than the defective LED in the first LED group to the carrier; or transferring the LEDs to the carrier and repairing it on the carrier.

Abstract: An interposer, including a redistribution layer structure, first conductive terminals, and second conductive terminals, is provided. The first conductive terminals are disposed on a first surface and are electrically connected to the second conductive terminals. An orthographic projection area of the first conductive terminals on the redistribution layer structure is inside a circuit range outline. There is a first pitch between the adjacent first conductive terminals. The second conductive terminals are disposed on a second surface. An orthographic projection area of a first part of the second conductive terminals on the redistribution layer structure is inside the circuit range outline. An orthographic projection area of a second part of the second conductive terminals on the redistribution layer structure is outside the circuit range outline. There is a second pitch between the adjacent second conductive terminals. The second pitch is greater than the first pitch. A semiconductor package is also provided.

Abstract: A semiconductor device includes a first doped region in a substrate, wherein the first doped region has a first dopant type. The semiconductor device further includes a second doped region in the substrate, wherein the second doped region has a second dopant type opposite the first dopant type. The semiconductor device further includes a silicide structure on the substrate, wherein the silicide structure includes a main body and a silicide extension. The semiconductor device further includes a plurality of first gate structures on the substrate, wherein a space between adjacent gate structures of the plurality of first gate structures includes a first area and a second area, the silicide extension extends into the first area, the first doped region is in the substrate below the first area, and the second doped region is in the substrate below the second area.

Abstract: An integrated circuit includes an array of first-type active-region structures and an array of second-type active-region structures extending in a first direction between a first vertical zone-boundary of a first keep-out zone and the second vertical zone-boundary of a second keep-out zone. The integrated circuit also includes an array of first-side boundary cells aligned with the first vertical zone-boundary and an array of second-side boundary cells aligned with the second vertical zone-boundary. In the array of first-side boundary cells, a first-side boundary cell has a first ESD protection circuit and a pick-up region. In the array of second-side boundary cells, a second-side boundary cell has a second ESD protection circuit.

Abstract: An interface of integrated circuit (IC) die includes a plurality of the contact elements formed as a contact element pattern corresponding to a parallel bus. The contact elements are arranged in an array of rows and columns and divided into a transmitting group and a receiving group. The contact elements of the transmitting group have a first contact element sequence and the contact elements of the receiving group have a second contact element sequence, the first contact element sequence is identical to the second contact element sequence. The contact elements with the first contact element sequence and the second contact element sequence are matched when the contact element pattern is geometrically rotated by 180° with respect to a row direction and a column direction.

Abstract: A manufacturing method of a semiconductor packaging device is provided, and the manufacturing method includes steps as follows. A working chip is soldered on one surface of a wiring board so that an working circuit inbuilt inside a chip body of the working chip is electrically connected to the wiring board. A silicon thermal conductivity element is soldered on one surface of a heat-dissipating metal lid. The heat-dissipating metal lid is fixedly covered on the wiring board such that the silicon thermal conductivity element is sandwiched between the chip body and the heat-dissipating metal lid, and the silicon thermal conductivity element is electrically isolated from the working circuit of the chip body and the wiring board.

Abstract: An interposer, including a redistribution layer structure, first conductive terminals, and second conductive terminals, is provided. The first conductive terminals are disposed on a first surface and are electrically connected to the second conductive terminals. An orthographic projection area of the first conductive terminals on the redistribution layer structure is inside a circuit range outline. There is a first pitch between the adjacent first conductive terminals. The second conductive terminals are disposed on a second surface. An orthographic projection area of a first part of the second conductive terminals on the redistribution layer structure is inside the circuit range outline. An orthographic projection area of a second part of the second conductive terminals on the redistribution layer structure is outside the circuit range outline. There is a second pitch between the adjacent second conductive terminals. The second pitch is greater than the first pitch. A semiconductor package is also provided.

Abstract: A method for testing electronic products implemented in an electronic device includes selecting a serial port connected with a slave device in serial communication with a product under test. An activation instruction is transmitted to the slave device, and the electronic product is started through the slave device. Data stored in at least one register of the electronic product and a state of the electronic product is obtained and a capacitance of at least one capacitor in the electronic product is measured. When the electronic product is found to be in an abnormal state, determining a cause of abnormality according to data of the electronic product and the capacitance of the at least one capacitor.

Abstract: A circuit board device includes a multilayer structure, a main ground area and a circuit module. The multilayer structure includes a plurality of plates. The main ground area is arranged in the multilayer structure. The circuit module includes a differential signal circuit and a surrounding circuit module. The differential signal circuit is located in the multilayer structure, and includes a positive signal pad and a negative signal pad. The positive signal pad is located on a configuration surface of one of the plates. The negative signal pad is located on the disposition surface, and is separated from the positive signal pad. The surrounding circuit module is located on the disposition surface, and electrically connected to the main ground area. The surrounding circuit module surrounds the positive signal pad and the negative signal pad in an enclosing way, and is physically separated from the differential signal circuit.

Abstract: A manufacturing method of a semiconductor packaging device is provided, and the manufacturing method includes steps as follows. A working chip is soldered on one surface of a wiring board so that an working circuit inbuilt inside a chip body of the working chip is electrically connected to the wiring board. A silicon thermal conductivity element is soldered on one surface of a heat-dissipating metal lid. The heat-dissipating metal lid is fixedly covered on the wiring board such that the silicon thermal conductivity element is sandwiched between the chip body and the heat-dissipating metal lid, and the silicon thermal conductivity element is electrically isolated from the working circuit of the chip body and the wiring board.

Abstract: An optical integration device includes a first circuit layer comprising a first surface adjacent a first diffractive layer, the first diffractive layer arranged on a side of the first circuit layer along a first direction, and a first connecting pad electrically connected with the first circuit layer through a first conductive member. The optical integration device includes a side surface extending along the first direction. The side surface defines a first concavity extending through the first diffractive layer along the first direction. The first connecting pad includes a first mounting member connected with the side surface, and a first convex member extending from the first mounting member and received in the first concavity. The first conductive member includes a first conductive part arranged between the side surface and the first mounting member, and a second conductive part arranged between the first surface and the first convex member.

Abstract: A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board.

Abstract: A semiconductor packaging device includes a wiring board, a working chip, a heat-dissipating metal lid and a silicon thermal conductivity element. The working chip is mounted on the wiring board, and in-built with an working circuit therein. The silicon thermal conductivity element is thermally coupled to the working chip and the heat-dissipating metal lid, and is electrically isolated from the working circuit and the wiring board.