Abstract: A method of fabricating cup shape cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells is disclosed. The cup shape capacitor shape is achieved by first depositing a first polysilicon layer on a silicon substrate; a third dielectric layer is then formed overlaying the first polysilicon layer, and defined third dielectric crowns by the conventional lithography and etching techniques; a second polysilicon layer is deposited overlaying the third dielectric crowns and first polysilicon layer; the first polysilicon and second polysilicon layers are then vertically anisotropically etchback to define storage nodes of the cylindrical capacitors; the third dielectric crowns are removed; finally, the capacitor dielectric layer and the polysilicon top plate of the capacitor are formed to complete the cup shape cylindrical capacitor formation for high density DRAM applications.

Abstract: A method for fabricating a capacitor electrode on a semiconductor substrate includes the steps of: forming a conducting layer over the semiconductor substrate; forming a photoresist layer over the conducting layer; pattering the photoresist layer through an interfering exposure step; and pattering the conducting layer using the patterned photoresist layer as a mask, thereby forming a capacitor electrode.

Abstract: The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact.

Abstract: A method for fabricating a DRAM cell having a crown-type capacitor over a semiconductor substrate is disclosed.

Abstract: A method of fabricating a capacitor plate constitutes first providing a substrate. Then, first insulating layer is formed over the substrate. Sequentially, a buffering layer and a second insulating layer, both of which constitute a stacked structure, are formed over the first insulating layer. Next, the stacked structure is patterned into an opening thereby exposing a portion of the first insulating layer therethrough. Subsequently, conducting spacers are formed on the sidewalls of the opening. The second insulating layer is thereafter removed, and simultaneously a portion of the first insulating layer not covered by the buffering layer and the conducting spacers are removed to form a contact window, thereby exposing a portion of the substrate therethrough. Then, a conducting layer is conformably deposited over the substrate, and thereafter etched away until a portion of the buffering layer is exposed. Finally, the exposed buffering layer is removed.

Abstract: The present invention provides a method for fabricating a storage plate of a semiconductor capacitor. A conductive layer is first formed on a semiconductor substrate. A glue layer is formed on the conductive layer. A plurality of micro masking-balls are then spread onto the surface of the glue layer. Using these micro masking-balls as masks, the glue layer is etched to expose a portion surface of the conductive layer. Using the remaining glue layer as a mask, the conductive layer is etched to form a bristle-shaped conductive layer. After that, the glue layer and micro masking-balls are removed, thereby allowing the remaining bristle-shaped conductive layer to form a storage plate of a semiconductor capacitor.

Abstract: The present invention discloses a DRAM structure with multiple memory cells sharing the same bit-line contact.

Abstract: A method of fabricating a rugged capacitor structure of high density Dynamic Random Access Memory (DRAM) cells is disclosed. First, MOSFETs, wordlines and bitlines are formed on a semiconductor silicon substrate. Next, a dielectric layer and a doped polysilicon layer are sequentially deposited over the entire silicon substrate. The dielectric layer and doped polysilicon layer are then partially etched to open source contact windows. Then, a polysilicon layer is deposited overlaying the doped polysilicon layer and filling into the source contact windows. Next, the polysilicon layer and doped polysilicon layers are partially etched to define bottom electrodes of the capacitors. Next, tilt angle implantation is performed to implant impurities into top surface and four sidewalls of the polysilicon layer and doped polysilicon layer. Next, a rugged polysilicon layer is deposited overlaying the polysilicon, doped polysilicon and third dielectric layers.

Abstract: A high performance thin film transistor structure which includes a pixel electrode layer formed after a passivation step such that electrical connections can be made to a source electrode and to overlap a channel length of the transistor. As a result, the effective channel length can be reduced and the occurrence of short-circuiting is also minimized in densely packed devices. The pixel electrode can be formed of a non-transparent metallic material to serve as a light shield such that the thin film transistor can be most suitably used in a liquid crystal display device.

Abstract: A thin film liquid crystal display, having a high aperture ratio, is described. The display has been designed so as to reduce the incidence of short circuits between its various parts. This has been achieved by modifying the structure of the lower electrode of the storage capacitor. The lower electrode is formed in the shape of a hollow square, two non-adjacent sides of the hollow square being at the level of the gate electrode, the other two sides of the hollow square being at the level of the data line. Two different means for providing electrical contact between all four sides of said lower capacitor electrode are described.

Abstract: The electric circuit of a Liquid Crystal Display normally includes a common electrode comprising a material such as indium-tin-oxide that has high resistivity and hence high series resistance. Said series resistance is significantly reduced by the design taught in the present invention wherein an electrically conductive black matrix is located so as to be in contact with the common electrode. Additionally, said design reduces the level of light reflected back in the direction of viewing, thereby improving the contrast level of the display.

Abstract: A thin film liquid crystal display, having a high aperture ratio, is described. Said display has been designed so as to reduce the incidence of short circuits between its various parts.This has been achieved by modifying the structure of the lower electrode of the storage capacitor. Said lower electrode is formed in the shape of a hollow square, two non-adjacent sides of said hollow square being at the level of the gate electrode, the other two sides of the hollow square being at the level of the data line. Two different means for providing electrical contact between all four sides of said lower capacitor electrode are described.A process for manufacturing the display is described.