Patents by Inventor Jia-Wei Fang
Jia-Wei Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230185280Abstract: An integrated circuit (IC) configurable to perform adaptive thermal ceiling control in a per-functional-block manner, an associated main circuit, an associated electronic device and an associated thermal control method are provided. The IC may include a plurality of hardware circuits arranged to perform operations of a first functional block, and at least one thermal control circuit. At least one temperature sensor is coupled with the first functional block to detect temperature and to generate at least one temperature sensing result of the first functional block.Type: ApplicationFiled: November 23, 2022Publication date: June 15, 2023Applicant: MEDIATEK INC.Inventors: Chih-Fu Tsai, Yu-Chia Chang, Bo-Jiun Yang, Yen-Hwei Hsieh, Shun-Yao Yang, Jia-Wei Fang, Ta-Chang Liao, Tai-Yu Chen
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Publication number: 20220334558Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.Type: ApplicationFiled: September 30, 2021Publication date: October 20, 2022Inventors: Bo-Jr Huang, Jia-Wei Fang, Jia-Ming Chen, Ya-Ting Chang, Chien-Yuan Lai, Cheng-Yuh Wu, Yi-Pin Lin, Wen-Wen Hsieh, Min-Shu Wang
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Patent number: 10109566Abstract: A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.Type: GrantFiled: May 9, 2017Date of Patent: October 23, 2018Assignee: MEDIATEK INC.Inventors: Jia-Wei Fang, Tzu-Hung Lin
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Patent number: 10067000Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.Type: GrantFiled: September 16, 2015Date of Patent: September 4, 2018Assignee: MEDIATEK INC.Inventors: Bo-Jr Huang, Yi-Feng Chen, Jia-Wei Fang
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Patent number: 9904752Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.Type: GrantFiled: December 31, 2015Date of Patent: February 27, 2018Assignee: MEDIATEK INC.Inventors: Zwei-Mei Lee, Bo-Jr Huang, Chi-Jih Shih, Jia-Wei Fang
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Patent number: 9904751Abstract: The invention provides a method of designing an integrated circuit. The method includes providing a physical layout group including a first layout corresponding to a first die having a first function. A second layout corresponds to an interposer configured for the first die connected thereon. The first physical layout group is partitioned into a first physical layout partition according to the first function. A first automatic place-and-route (APR) process is performed to obtain a first hierarchical layout according to the first physical layout partition. A first verification is performed on the first hierarchical layout.Type: GrantFiled: June 18, 2015Date of Patent: February 27, 2018Assignee: MEDIATEK INC.Inventor: Jia-Wei Fang
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Publication number: 20170243814Abstract: A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface of the flip-chip. Vias are disposed on the second bump pads. The first bump pads have a pad size that is smaller than that of the second bump pads. An underfill layer is disposed between the flip-chip and the substrate to surround the vias. The underfill layer is in direct contact with a surface of each of the first bump pads.Type: ApplicationFiled: May 9, 2017Publication date: August 24, 2017Inventors: Jia-Wei Fang, Tzu-Hung Lin
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Patent number: 9679830Abstract: A semiconductor package includes a packaging substrate having a first surface and a second surface opposite to the first surface; and a semiconductor die assembled on the first surface of the packaging substrate. The semiconductor die includes a plurality of first bump pads and second bump pads on an active surface of the semiconductor die, a plurality of first copper pillars on the first bump pads, and a plurality of second copper pillars on the second bump pads. The first copper pillars have a diameter that is smaller than that of the second copper pillars.Type: GrantFiled: August 19, 2015Date of Patent: June 13, 2017Assignee: MEDIATEK INC.Inventors: Jia-Wei Fang, Tzu-Hung Lin
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Patent number: 9660017Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.Type: GrantFiled: October 29, 2015Date of Patent: May 23, 2017Assignee: MEDIATEK INC.Inventors: Chao-Yang Yeh, Chee-Kong Ung, Tzu-Hung Lin, Jia-Wei Fang
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Patent number: 9589092Abstract: A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.Type: GrantFiled: November 18, 2014Date of Patent: March 7, 2017Assignee: MEDIATEK INC.Inventors: Jia-Wei Fang, Chi-Jih Shih, Shen-Yu Huang
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Patent number: 9552452Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.Type: GrantFiled: March 31, 2016Date of Patent: January 24, 2017Assignee: MEDIATEK INC.Inventors: Jia-Wei Fang, Shen-Yu Huang
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Publication number: 20160343796Abstract: A capacitor structure includes first and second interdigitated conductive elements formed over different portions of a semiconductor substrate, and a dielectric layer formed between the first and second interdigitated conductive elements. The first interdigitated conductive element that is formed includes a first base portion and a plurality of first protrusion portions. The second interdigitated conductive element includes a second base portion and a plurality of second protrusion portions. The second protrusion portions of the second interdigitated conductive element are interleaved with the first protrusion portions of the first interdigitated conductive element.Type: ApplicationFiled: May 19, 2016Publication date: November 24, 2016Inventors: Bo-Jr HUANG, Jia-Wei FANG
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Patent number: 9490808Abstract: A sensing circuit includes a delay chain and a decoder. The delay chain includes at least one delay unit, at least one cascading switch, and at least one feedback switch. The delay unit generates a delay signal according to an input signal and a reset signal. The cascading switch selectively passes the delay signal according to a control signal. The feedback switch selectively forms a feedback path of the delay unit according to the control signal. The decoder generates an output signal according to the delay signal. The delay unit is supplied by a work voltage. If the work voltage has noise, the noise will be detectable by analyzing the output signal of the decoder.Type: GrantFiled: October 29, 2015Date of Patent: November 8, 2016Assignee: MEDIATEK INC.Inventors: Bo-Jr Huang, Jia-Wei Fang
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Publication number: 20160217244Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.Type: ApplicationFiled: March 31, 2016Publication date: July 28, 2016Inventors: Jia-Wei Fang, Shen-Yu Huang
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Publication number: 20160217243Abstract: A method for distributing power in the layout of an integrated circuit is provided. The integrated circuit includes at least one macro block. A first physical layout of the macro block is obtained, wherein the macro block includes a plurality of standard cells. The first physical layout is divided into a plurality of partitions according to an IR simulation result of the first physical layout. A plurality of power isolation cells are inserted between the partitions. A second physical layout is obtained according to the partitions and the power isolation cells. A macro placement of the macro block is obtained according to the second physical layout. Each of the partitions further includes a low drop out (LDO) regulator.Type: ApplicationFiled: December 31, 2015Publication date: July 28, 2016Inventors: Zwei-Mei LEE, Bo-Jr HUANG, Chi-Jih SHIH, Jia-Wei FANG
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Publication number: 20160211318Abstract: A microelectronic package includes a packaging substrate having a chip mounting surface; a chip mounted on the chip mounting surface of the packaging substrate with the chip's active surface facing down to the chip mounting surface; a plurality of input/output (I/O) pads distributed on the active surface of the chip; and a discrete passive element mounted on the active surface of the chip. The discrete passive element may be a decoupling capacitor, a resistor, or an inductor.Type: ApplicationFiled: October 29, 2015Publication date: July 21, 2016Inventors: Chao-Yang Yeh, Chee-Kong Ung, Tzu-Hung Lin, Jia-Wei Fang
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Publication number: 20160203253Abstract: The invention provides a method of designing an integrated circuit. The method includes providing a physical layout group including a first layout corresponding to a first die having a first function. A second layout corresponds to an interposer configured for the first die connected thereon. The first physical layout group is partitioned into a first physical layout partition according to the first function. A first automatic place-and-route (APR) process is performed to obtain a first hierarchical layout according to the first physical layout partition. A first verification is performed on the first hierarchical layout.Type: ApplicationFiled: June 18, 2015Publication date: July 14, 2016Inventor: Jia-Wei FANG
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Publication number: 20160197071Abstract: The invention provides an integrated circuit device. The integrated circuit device includes a semiconductor substrate. An isolation structure is positioned in the semiconductor substrate. A first electrode and a second electrode are positioned on the semiconductor substrate and coupled to different voltage supplies. The first electrode laterally or parallelly overlaps the second electrode. The first electrode and the second electrode vertically overlap the isolation structure. As a result, leakage current is mitigated or eliminated so that the reliability and performance of the integrated circuit device are improved.Type: ApplicationFiled: September 22, 2015Publication date: July 7, 2016Inventors: Chao-Yang YEH, Yi-Feng CHEN, Jia-Wei FANG, Yao-Tsung HUANG, Ming-Cheng LEE
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Publication number: 20160190083Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.Type: ApplicationFiled: March 2, 2015Publication date: June 30, 2016Inventors: Jia-Wei Fang, Shen-Yu Huang
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Patent number: 9379079Abstract: The present invention provides a flip chip scheme and a method of forming the flip chip scheme. The flip chip scheme comprises: a plurality of bumps, some of the bumps arranged in a first pattern, respectively, and some of the bumps arranged in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps. The method comprises: arranging some of the bumps in a first pattern, respectively, and arranging some of the bumps in a second pattern different from the first pattern, respectively; wherein the first pattern is an equilateral triangle arranged by three bumps, and the second pattern is a square arranged by four bumps.Type: GrantFiled: March 2, 2015Date of Patent: June 28, 2016Assignee: MEDIATEK INC.Inventors: Jia-Wei Fang, Shen-Yu Huang