Abstract: The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.

Abstract: A sensing circuit includes a delay chain and a decoder. The delay chain includes at least one delay unit, at least one cascading switch, and at least one feedback switch. The delay unit generates a delay signal according to an input signal and a reset signal. The cascading switch selectively passes the delay signal according to a control signal. The feedback switch selectively forms a feedback path of the delay unit according to the control signal. The decoder generates an output signal according to the delay signal. The delay unit is supplied by a work voltage. If the work voltage has noise, the noise will be detectable by analyzing the output signal of the decoder.

Abstract: A semiconductor package includes a packaging substrate having a first surface and a second surface opposite to the first surface; and a semiconductor die assembled on the first surface of the packaging substrate. The semiconductor die includes a plurality of first bump pads and second bump pads on an active surface of the semiconductor die, a plurality of first copper pillars on the first bump pads, and a plurality of second copper pillars on the second bump pads. The first copper pillars have a diameter that is smaller than that of the second copper pillars.

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.

Abstract: A method for co-designing a flip-chip and an interposer is provided. Information regarding I/O pads, power pins and IR constraints of the flip-chip is obtained. A bump planning procedure is performed to obtain a total number of micro bumps of the flip-chip according to the information, and obtain a minimum conductance of each of the power pins of the flip-chip according to a bump placement of the micro bumps of the flip-chip. A chip-interposer routing procedure is performed to obtain a Re-Distribution Layer (RDL) routing of the flip-chip and an interposer routing of the interposer according to the minimum conductance of the power pins of the flip-chip.

Abstract: The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.